| Citation: |
Zhang Xiaowei, Hu Qingsheng. A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture[J]. Journal of Semiconductors, 2011, 32(4): 045009. doi: 10.1088/1674-4926/32/4/045009
Zhang X W, Hu Q S. A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture[J]. J. Semicond., 2011, 32(4): 045009. doi: 10.1088/1674-4926/32/4/045009.
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A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture
doi: 10.1088/1674-4926/32/4/045009
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Abstract
A fully pipelined 10 B/8 B decoder is presented with shorter critical path than before, and so its speed is improved greatly. Based on the proposed architecture, a 10 B/8 B decoder is implemented based on standard cells in 0.18 μm CMOS technology with a core area of 375 × 375 μ m2. Measurement results show that the decoder works well and its speed can be up to 6.25 Gbps. At a 1.8 V power supply, the total power consumption is 21.6 mW during 6.25 Gbps operation and the peak-to-peak jitter in the eye diagram is 177.8 ps.-
Keywords:
- SerDes,
- 10 B/8 B decoder,
- pipelined,
- high-speed
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References
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Proportional views
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