| Citation: |
Li Yongliang, Xu Qiuxia. Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal–oxide–semiconductor devices[J]. Journal of Semiconductors, 2011, 32(7): 076001. doi: 10.1088/1674-4926/32/7/076001
Li Y L, Xu Q X. Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal–oxide–semiconductor devices[J]. J. Semicond., 2011, 32(7): 076001. doi: 10.1088/1674-4926/32/7/076001.
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Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal–oxide–semiconductor devices
doi: 10.1088/1674-4926/32/7/076001
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Abstract
A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal–oxide–semiconductor (CMOS) devices is investigated. Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile. First, a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate. Then different BCl3-based plasmas are applied to etch the TaN metal gate and find that BCl3/Cl2/O2/Ar plasma is a suitable choice to get a vertical TaN profile. Moreover, considering that Cl2 almost has no selectivity to Si substrate, BCl3/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl3/Cl2/O2/Ar plasma. Finally, we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.-
Keywords:
- TaN metal gate,
- HfSiON high-k,
- plasma etching,
- selectivity,
- integration
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References
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] -
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