SEMICONDUCTOR INTEGRATED CIRCUITS

A 5 Gb/s transceiver in 0.13 μm CMOS for PCIE2.0

Luo Gang, Gao Changping and Zeng Xianjun

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Abstract: This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC's 0.13 μm CMOS technology. The active area of the transceiver is 0.016 mm2 and it consumes a total of 150 mW power at a 1.2 V supply voltage. The transmitter uses two stage pre-emphasis circuits with active inductors, reducing inter-symbol interference and extended bandwidth;the receiver uses a time-domain adaptive equalizer, the circuit uses an inductive peaking technique and extends the bandwidth, and the use of active inductors reduces the circuit area and power consumption effectively. The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps, the output signal swing of the transmitter is 350 mV with jitter of 14 ps, the eye opening of the receiver is 135 mV and the eye width is 0.56 UI. The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.

Key words: serial linkCMLpre-emphasisadaptive equalizerinductive peakingactive inductor

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    Received: 18 August 2015 Revised: 08 March 2011 Online: Published: 01 August 2011

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      Luo Gang, Gao Changping, Zeng Xianjun. A 5 Gb/s transceiver in 0.13 μm CMOS for PCIE2.0[J]. Journal of Semiconductors, 2011, 32(8): 085013. doi: 10.1088/1674-4926/32/8/085013 Luo G, Gao C P, Zeng X J. A 5 Gb/s transceiver in 0.13 μm CMOS for PCIE2.0[J]. J. Semicond., 2011, 32(8): 085013. doi: 10.1088/1674-4926/32/8/085013.Export: BibTex EndNote
      Citation:
      Luo Gang, Gao Changping, Zeng Xianjun. A 5 Gb/s transceiver in 0.13 μm CMOS for PCIE2.0[J]. Journal of Semiconductors, 2011, 32(8): 085013. doi: 10.1088/1674-4926/32/8/085013

      Luo G, Gao C P, Zeng X J. A 5 Gb/s transceiver in 0.13 μm CMOS for PCIE2.0[J]. J. Semicond., 2011, 32(8): 085013. doi: 10.1088/1674-4926/32/8/085013.
      Export: BibTex EndNote

      A 5 Gb/s transceiver in 0.13 μm CMOS for PCIE2.0

      doi: 10.1088/1674-4926/32/8/085013
      Funds:

      Natural Science Foundation of China

      • Received Date: 2015-08-18
      • Accepted Date: 2011-01-31
      • Revised Date: 2011-03-08
      • Published Date: 2011-07-19

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