| Citation: |
Guo Ting, Li Zhiqun, Li Qin, Wang Zhigong. A 7-27 GHz DSCL divide-by-2 frequency divider[J]. Journal of Semiconductors, 2012, 33(10): 105006. doi: 10.1088/1674-4926/33/10/105006
Guo T, Li Z Q, Li Q, Wang Z G. A 7-27 GHz DSCL divide-by-2 frequency divider[J]. J. Semicond., 2012, 33(10): 105006. doi: 10.1088/1674-4926/33/10/105006.
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A 7-27 GHz DSCL divide-by-2 frequency divider
doi: 10.1088/1674-4926/33/10/105006
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Abstract
This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic (DSCL) structure formed with two dynamic-loading master-slave D latches, which enables high frequency operation and low power consumption. This divider exhibits a wide locking range from 7-27 GHz and the minimum power consumption is only 1.22 mW from a 1.2 V supply. The input sensitivity is as low as -25.4 dBm across the operating frequency range. This chip occupies 685 × 430 μm2 area with two on-chip spiral inductors in 90 nm CMOS process.-
Keywords:
- broadband
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References
[1] [2] [3] [4] [5] [6] [7] [8] [9] -
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