Abstract: An analog baseband circuit for a direct conversion wireless local area network (WLAN) transceiver in a standard 0.13-μm CMOS occupying 1.26 mm² is presented. The circuit consists of active-RC receiver (RX) 4th order elliptic lowpass filters (LPFs), transmitter (TX) 3rd order Chebyshev LPFs, RX programmable gain amplifiers (PGAs) with DC offset cancellation (DCOC) servo loops, and on-chip output buffers. The RX baseband gain can be programmed in the range of -11 to 49 dB in 2 dB steps with 50-30.2 nV/√Hz input referred noise (IRN) and a 21 to -41 dBm in-band 3rd order interception point (IIP3). The RX/TX LPF cutoff frequencies can be switched between 5 MHz, 10 MHz, and 20 MHz to fulfill the multimode 802.11b/g/n requirements. The TX baseband gain of the I/Q paths are tuned separately from -1.6 to 0.9 dB in 0.1 dB steps to calibrate TX I/Q gain mismatches. By using an identical integrator based elliptic filter synthesis method together with global compensation applied to the LPF capacitor array, the power consumption of the RX LPF is considerably reduced and the proposed chip draws 26.8 mA/8 mA by the RX/TX baseband paths from a 1.2 V supply.

Key words: WLAN