| Citation: |
Cai Hua. A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB[J]. Journal of Semiconductors, 2012, 33(11): 115013. doi: 10.1088/1674-4926/33/11/115013
Cai H. A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB[J]. J. Semicond., 2012, 33(11): 115013. doi: 10.1088/1674-4926/33/11/115013.
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A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB
doi: 10.1088/1674-4926/33/11/115013
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Abstract
This paper describes the design of a 14-bit 20 Msps analog-to-digital converter (ADC), implemented in 0.18 μm CMOS technology, achieving 11.2 effective number of bits at Nyquist rate. An improved SHA-less structure and op-amp sharing technique is adopted to significantly reduce the power. The proposed ADC consumes only 166 mW under 1.8 V supply. A fast background calibration is utilized to ensure the overall ADC linearity.-
Keywords:
- CMOS
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References
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] -
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