| Citation: |
Meng Lingkuan, Yin Huaxiang, Chen Dapeng, Ye Tianchun. Metal gate etch-back planarization technology[J]. Journal of Semiconductors, 2012, 33(3): 036001. doi: 10.1088/1674-4926/33/3/036001
Meng L K, Yin H X, Chen D P, Ye T C. Metal gate etch-back planarization technology[J]. J. Semicond., 2012, 33(3): 036001. doi: 10.1088/1674-4926/33/3/036001.
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Metal gate etch-back planarization technology
doi: 10.1088/1674-4926/33/3/036001
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Abstract
Planarization used in a gate-last CMOS device was successfully developed by particular technologies of SOG two-step plasma etch-back plus one special etch-back step for SOG/SiO2 interface trimming. The within-the-wafer ILD thickness non-uniformity can reach 4.19% with a wafer edge exclusion of 5 mm. SEM results indicated that there was little “dish effect” on the 0.4 μm gate-stack structure and finally achieved a good planarization profile on the whole substrate. The technology provided a CMP-less process basis for sub-100 nm high-k/metal gate-last CMOS integration.-
Keywords:
- metal gate,
- plasma etch-back,
- planarization,
- spin on glass
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References
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] -
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