Abstract: We have presented an analysis of the gate leakage current of the IP3 static random access memory (SRAM) cell structure when the cell is in idle mode (performs no data read/write operations) and active mode (performs data read/write operations), along with the requirements for the overall standby leakage power, active write and read powers. A comparison has been drawn with existing SRAM cell structures, the conventional 6T, PP, P4 and P3 cells. At the supply voltage, V_DD = 0.8 V, a reduction of 98%, 99%, 92% and 94% is observed in the gate leakage current in comparison with the 6T, PP, P4 and P3 SRAM cells, respectively, while at V_DD = 0.7 V, it is 97%, 98%, 87% and 84%. A significant reduction is also observed in the overall standby leakage power by 56%, the active write power by 44% and the active read power by 99%, compared with the conventional 6T SRAM cell at V_DD = 0.8 V, with no loss in cell stability and performance with a small area penalty. The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor (CMOS) technology, t_ox = 2.4 nm, V_thn = 0.22 V, V_thp = 0.224 V, V_DD = 0.7 V and 0.8 V, at T = 300 K.

Key words: gate leakage, subthreshold leakage, low power, deep sub-micron, SRAM