| Citation: |
Yu Bo, Li Xiangyu, Chen Cong, Sun Yihe, Wu Liji, Zhang Xiangmin. An AES chip with DPA resistance using hardware-based random order execution[J]. Journal of Semiconductors, 2012, 33(6): 065009. doi: 10.1088/1674-4926/33/6/065009
Yu B, Li X Y, Chen C, Sun Y H, Wu L J, Zhang X M. An AES chip with DPA resistance using hardware-based random order execution[J]. J. Semicond., 2012, 33(6): 065009. doi: 10.1088/1674-4926/33/6/065009.
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An AES chip with DPA resistance using hardware-based random order execution
doi: 10.1088/1674-4926/33/6/065009
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Abstract
This paper presents an AES (advanced encryption standard) chip that combats differential power analysis (DPA) side-channel attack through hardware-based random order execution. Both decryption and encryption procedures of an AES are implemented on the chip. A fine-grained dataflow architecture is proposed, which dynamically exploits intrinsic byte-level independence in the algorithm. A novel circuit called an HMF (Hold-Match-Fetch) unit is proposed for random control, which randomly sets execution orders for concurrent operations. The AES chip was manufactured in SMIC 0.18 μm technology. The average energy for encrypting one group of plain texts (128 bits secrete keys) is 19 nJ. The core area is 0.43 mm2. A sophisticated experimental setup was built to test the DPA resistance. Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack. Compared with the corresponding fixed order execution, the hardware based random order execution is improved by at least 21 times the DPA resistance.-
Keywords:
- differential power analysis
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References
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] -
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