SEMICONDUCTOR INTEGRATED CIRCUITS

A 10 Gb/s burst-mode clock and data recovery circuit

Gu Gaowei, Zhu En, Lin Ye and Liu Wensong

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Abstract: We introduce a gated oscillator based on XONR/XOR cells and illustrate its working process. A half-rate BM-CDR circuit based on the proposed oscillator is designed, and the design is implemented in SMIC 0.13 μm CMOS technology occupying an area of 675 × 25 μm2. The measured results show that this circuit can recover clock and data from each 10 Gbit/s burst-mode data packet within 5 bits, and the recovered data pass eye-mask test defined in IEEE standard 802.3av.

Key words: 10G-EPONclock and data recoveryburst-modegated voltage-controlled-oscillatorfrequency locked loop

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    Received: 20 August 2015 Revised: 07 February 2012 Online: Published: 01 July 2012

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      Gu Gaowei, Zhu En, Lin Ye, Liu Wensong. A 10 Gb/s burst-mode clock and data recovery circuit[J]. Journal of Semiconductors, 2012, 33(7): 075011. doi: 10.1088/1674-4926/33/7/075011 Gu G W, Zhu E, Lin Y, Liu W S. A 10 Gb/s burst-mode clock and data recovery circuit[J]. J. Semicond., 2012, 33(7): 075011. doi: 10.1088/1674-4926/33/7/075011.Export: BibTex EndNote
      Citation:
      Gu Gaowei, Zhu En, Lin Ye, Liu Wensong. A 10 Gb/s burst-mode clock and data recovery circuit[J]. Journal of Semiconductors, 2012, 33(7): 075011. doi: 10.1088/1674-4926/33/7/075011

      Gu G W, Zhu E, Lin Y, Liu W S. A 10 Gb/s burst-mode clock and data recovery circuit[J]. J. Semicond., 2012, 33(7): 075011. doi: 10.1088/1674-4926/33/7/075011.
      Export: BibTex EndNote

      A 10 Gb/s burst-mode clock and data recovery circuit

      doi: 10.1088/1674-4926/33/7/075011
      Funds:

      Key Technology Research and Development Program of Jiangsu Province, Industry Part

      • Received Date: 2015-08-20
      • Accepted Date: 2011-11-30
      • Revised Date: 2012-02-07
      • Published Date: 2012-06-27

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