| Citation: |
Yang Zhaonian, Liu Hongxia, Li Li, Zhuo Qingqing. A novel high performance ESD power clamp circuit with a small area[J]. Journal of Semiconductors, 2012, 33(9): 095006. doi: 10.1088/1674-4926/33/9/095006
Yang Z N, Liu H X, Li L, Zhuo Q Q. A novel high performance ESD power clamp circuit with a small area[J]. J. Semicond., 2012, 33(9): 095006. doi: 10.1088/1674-4926/33/9/095006.
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A novel high performance ESD power clamp circuit with a small area
doi: 10.1088/1674-4926/33/9/095006
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Abstract
A MOSFET-based electrostatic discharge (ESD) power clamp circuit with only a 10 ns RC time constant for a 0.18-μm process is proposed. A diode-connected NMOSFET is used to maintain a long delay time and save area. The special structure overcomes other shortcomings in this clamp circuit. Under fast power-up events, the gate voltage of the clamp MOSFET does not rise as quickly as under ESD events, the special structure can keep the clamp MOSFET thoroughly off. Under a falsely triggered event, the special structure can turn off the clamp MOSFET in a short time. The clamp circuit can also reject the power supply noise effectively. Simulation results show that the clamp circuit avoids fast false triggering events such as a 30 ns/1.8 V power-up, maintains a 1.2 μs delay time and a 2.14 μs turn-off time, and reduces to about 70% of the RC time constant. It is believed that the proposed clamp circuit can be widely used in high-speed integrated circuits. -
References
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] -
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