J. Semicond. > 2013, Volume 34 > Issue 10 > 105001, doi: 10.1088/1674-4926/34/10/105001
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SEMICONDUCTOR INTEGRATED CIRCUITS

A 55 nm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers with low noise filters

Mingyi Chen, Xiaojie Chu, Peng Yu, Jun Yan and Yin Shi

+ Author Affiliations

 Corresponding author: Chen Mingyi, tjucmy@126.com

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Abstract: A fully integrated Δ Σ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network (WLAN) transceivers. A low noise filter, occupying a small die area, whose power supply is given by a high PSRR and low noise LDO regulator, is integrated on chip. The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm2 excluding PAD. Measurement results show that in all channels, the phase noise of the synthesizer achieves -99 dBc/Hz and -119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz. The integrated RMS phase error is no more than 0.6°. The proposed synthesizer consumes a total power of 15.6 mW.

Key words: WLAN IEEE 802.11 b/g, frequency synthesizer, low noise filter, ΔΣ modulator



[1]
Jones C G, Beghein C C. Low noise filter. US Patent, No. 6891412 B1, 2005
[2]
Tham K M, Nagaraj K. A low supply voltage high PSRR voltage reference in CMOS process. IEEE J Solid-State Circuits, 1995, 30(5):586 doi: 10.1109/4.384173
[3]
Jian H Y, Xu Z, Wu Y C, et al. A fractional-N PLL for multiband (0.8-6 GHz) communications using binary-weighted D/A differentiator and offset-frequency Δ-Σ modulator. IEEE J Solid-State Circuits, 2010, 45(4):768 https://www.infona.pl/resource/bwmeta1.element.ieee-art-000005437492
[4]
Kondou M, Matsuda A, Yamazaki H, et al. A 0.3 mm2 90-to-770 MHz fractional synthesizer for a digital TV tuner. International Solid-State Circuits Conference, 2010:247 http://ieeexplore.ieee.org/document/5433939/
[5]
Shin J, Shin H. A 1.9-3.8 GHz ΔΣ fractional-N PLL frequency synthesizer with fast auto-calibration of loop bandwidth and VCO frequency. IEEE J Solid-State Circuits, 2012, 47(3):665 http://ieeexplore.ieee.org/Xplore/home.jsp
Fig. 1.  Block diagram of the proposed $\Delta \sum $ fractional-N frequency synthesizer.

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Fig. 2.  (a) Traditional low pass loop filter. (b) The proposed low noise filter

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Fig. 3.  (a) Magnitude and phase frequency response of the traditional low pass loop filter and low noise filter. (b) Output noise voltage of the traditional low pass loop filter and low noise filter.

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Fig. 4.  (a) Schematic of the LDO regulator. (b) Schematic of the bandgap reference.

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Fig. 5.  (a) Simulation results of the PSRR of the LDO regulator. (b) Simulation results of the output noise of the LDO regulator

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Fig. 6.  (a) Schematic of the VCO. (b) Schematic of the VCO buffer.

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Fig. 7.  Schematic architecture of the charge pump and the rail to rail operating amplifier.

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Fig. 8.  (a) Block diagram of the muli-modulas divider. (b) Block diagram of the $\Delta \sum $ modulator

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Fig. 9.  Die photograph of the synthesizer.

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Fig. 10.  Phase noise performance of 1.62467 GHz (measured at the output of the VCO buffer).

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Fig. 11.  Phase noise performance of 2.437 GHz (measured at the output of the PA).

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Fig. 12.  Frequency spectrum of 1.6246 GHz (measured at the output of the VCO buffer).

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Fig. 13.  Phase noise performance of all channels (measured at the output of the VCO buffer).

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Fig. 14.  RMS phase error performance of all channels (measured at the output of the VCO buffer)

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Fig. 15.  Phase noise performance while enabling and disabling the LDO regulator.

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Table 1.   Performance comparison with other related works
[1]
Jones C G, Beghein C C. Low noise filter. US Patent, No. 6891412 B1, 2005
[2]
Tham K M, Nagaraj K. A low supply voltage high PSRR voltage reference in CMOS process. IEEE J Solid-State Circuits, 1995, 30(5):586 doi: 10.1109/4.384173
[3]
Jian H Y, Xu Z, Wu Y C, et al. A fractional-N PLL for multiband (0.8-6 GHz) communications using binary-weighted D/A differentiator and offset-frequency Δ-Σ modulator. IEEE J Solid-State Circuits, 2010, 45(4):768 https://www.infona.pl/resource/bwmeta1.element.ieee-art-000005437492
[4]
Kondou M, Matsuda A, Yamazaki H, et al. A 0.3 mm2 90-to-770 MHz fractional synthesizer for a digital TV tuner. International Solid-State Circuits Conference, 2010:247 http://ieeexplore.ieee.org/document/5433939/
[5]
Shin J, Shin H. A 1.9-3.8 GHz ΔΣ fractional-N PLL frequency synthesizer with fast auto-calibration of loop bandwidth and VCO frequency. IEEE J Solid-State Circuits, 2012, 47(3):665 http://ieeexplore.ieee.org/Xplore/home.jsp

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    Received: 11 March 2013 Revised: 10 April 2013 Online: Published: 01 October 2013

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      Article Navigation >  Journal of Semiconductors  > 2013  >  34(10): 105001
      Mingyi Chen, Xiaojie Chu, Peng Yu, Jun Yan, Yin Shi. A 55 nm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers with low noise filters[J]. Journal of Semiconductors, 2013, 34(10): 105001. doi: 10.1088/1674-4926/34/10/105001 M Y Chen, X J Chu, P Yu, J Yan, Y Shi. A 55 nm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers with low noise filters[J]. J. Semicond., 2013, 34(10): 105001. doi: 10.1088/1674-4926/34/10/105001.Export: BibTex EndNote
      Citation:
      Mingyi Chen, Xiaojie Chu, Peng Yu, Jun Yan, Yin Shi. A 55 nm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers with low noise filters[J]. Journal of Semiconductors, 2013, 34(10): 105001. doi: 10.1088/1674-4926/34/10/105001

      M Y Chen, X J Chu, P Yu, J Yan, Y Shi. A 55 nm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers with low noise filters[J]. J. Semicond., 2013, 34(10): 105001. doi: 10.1088/1674-4926/34/10/105001.
      Export: BibTex EndNote
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      A 55 nm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers with low noise filters

      doi: 10.1088/1674-4926/34/10/105001

      • Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

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      • Corresponding author: Chen Mingyi, tjucmy@126.com
      • Received Date: 2013-03-11
      • Revised Date: 2013-04-10
      • Published Date: 2013-10-01

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