A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect

Sudhansu Kumar Pati; Kalyan Koley; Arka Dutta; N Mohankumar; Chandan Kumar Sarkar

doi:10.1088/1674-4926/34/11/114002

J. Semicond. > 2013, Volume 34 > Issue 11 > 114002, doi: 10.1088/1674-4926/34/11/114002

SEMICONDUCTOR DEVICES

A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect

Sudhansu Kumar Pati¹, Kalyan Koley¹, Arka Dutta¹, N Mohankumar² and Chandan Kumar Sarkar¹

+ Author Affiliations

Corresponding author: Sudhansu Kumar Pati,Email:

Abstract: In analog circuit design an important parameter, from the perspective of superior device performance, is linearity. The DG MOSFET in asymmetric mode operation has been found to present a better linearity. In addition to that it provides, at the discretion of analog circuit designer, an additional degree of freedom, by providing independent bias control for the front and the back gates. Here a non-quasi-static (NQS) small signal model for DGMOSFET with asymmetric gate bias is proposed for extracting the parameters of the device using TCAD simulations. The parameters extracted here for analysis are the intrinsic front and back gate to drain capacitance, C_gd1 and C_gd2, the intrinsic front and back distributed channel resistance, R_gd1 and R_gd2 respectively, the transport delay, τ_m, and the inductance, L_sd. The parameter extraction model for an asymmetric DG MOSFET is validated with pre-established extracted parameter data, for symmetric DG MOSFET devices, from the available literature. The device simulation is performed with respect to frequency up to 100 GHz.

Key words: asymmetric DGMOSFET, RF modeling, small signal analysis, parameter extraction

References

[1]	Suryagandh S S, Garg M, Woo J C S. A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs. IEEE Trans Electron Devices, 2004, 51(7):1122 doi: 10.1109/TED.2004.829872
[2]	Liang J, Xiao H, Huang R, et al. Design optimization of structural parameters in double gate MOSFETs for RF applications. Semicond Sci Technol, 2008, 23(5):1 doi: 10.1007/s10470-013-0164-1
[3]	Jiale L, Han X, Ru H, et al. Design optimization of structural parameters in double gate MOSFETs for RF applications. Semicond Sci Technol, 2008, 23:1 doi: 10.1007/s10470-013-0164-1
[4]	Savas K, Wei M. Optimization of RF linearity in DG-MOSFETs. IEEE Electron Device Lett, 2004, 25(5):308 doi: 10.1109/LED.2004.826539
[5]	Qiang C, Meindl J D. A comparative study of threshold variations in symmetric and asymmetric undoped double-gate MOSFETs. IEEE International SOI Conference, 2002:30 doi: 10.1007/978-3-319-01165-3_3/fulltext.html
[6]	Reddy G V, Kumar M J. Investigation of the novel attributes of a single-halo double gate SOI MOSFET:2D simulation study. Microelectron J, 2004, 35:761 doi: 10.1016/j.mejo.2004.06.003
[7]	Reddy M V R, Sharma D K, Patil M B, et al. Power-area evaluation of various double-gate RF mixer topologies. IEEE Electron Devices Lett, 2005, 26:664 doi: 10.1109/LED.2005.853632
[8]	Kaya S, Hamed H F A, Starzyk J A. Low-power tunable analog circuit blocks based on nanoscale double-gate MOSFETs. IEEE Trans Circuits Syst Ⅱ, 2007, 54(7):571 doi: 10.1109/TCSII.2007.895324
[9]	Pei G, Kan E C. Circuit design principles for independently driven double-gate MOSFETs. VLSI Tech Dig, Honolulu, HI, June 2002
[10]	Han J W, Kim C J, Choi Y K. Universal potential model in tied and separated double-gate MOSFETs with consideration of symmetric and asymmetric structure. IEEE Trans Electron Devices, 2008, 55(6):1472 doi: 10.1109/TED.2008.922492
[11]	International Technology Roadmaps for Semiconductor (ITRS). 2008
[12]	Sentaurus TCAD Manuals, Synopsys Inc. Mountain View, CA 94043, USA. Release C-2009.06; 2009
[13]	Esseni D, Mastrapasqua M, Celler G K, et al. Low field mobility of ultra-thin SOI N-and P-MOSFETs:measurements and implications on the performance of ultra-short MOSFETs. IEDM Tech Dig, 2000:671 http://www.academia.edu/27129756/Low_field_electron_and_hole_mobility_of_SOI_transistors_fabricated_on_ultrathin_silicon_films_for_deep_submicrometer_technology_application
[14]	Kang I M, Shin H. Non-quasi-static small-signal modeling and analytical parameter extraction of SOI FinFETs. IEEE Trans Nano Technol, 2006, 5(3):205 doi: 10.1109/TNANO.2006.869946
[15]	BSIM3v3.3.0 MOSFET Model-Users' Manual
[16]	Balestra F, Cristoloveanu S, Benachir M, et al. Double-gate silicon-on-insulator transistor with volume inversion:a new device with greatly enhanced performance. IEEE Electron Device Lett, 1987, 8:410 doi: 10.1109/EDL.1987.26677
[17]	Venkatesan S, Neudeck G V, Pierret R F. Double-gate operation and volume inversion in n-channel SOI MOSFET's. IEEE Electron Device Lett, 1992, 13:44 doi: 10.1109/55.144946
[18]	Balestra F. Comments on:double-gate operation and volume inversion in n-channel SOI MOSFET's. IEEE Electron Device Lett, 1992, 13:658 doi: 10.1109/55.192876
[19]	Frank D J, Laux S E, Fischetti M V. Monte Carlo simulation of a 30 nm dual-gate MOSFET:how short can Si go.Proc IEDM, San Francisco, CA, 1992:553 doi: 10.1007/s10825-009-0277-z
[20]	Omura Y, Nakashima S, Izumi K, et al. 0.1 m gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer. IEEE Trans Electron Devices, 1993, 40:1019 doi: 10.1109/16.210214
[21]	Fiegna C, Abramo A. Solution of Schrödinger and Poisson equation in single and double gate SOI MOS. Proc IEDM, San Francisco, CA, 1997:93 http://jeldev.org/16_R-Sharma.pdf

Fig. 1. The cross sectional view of double gate MOSFET. $t_{\rm si}$, $t_{\rm ox}$ and $t_{\rm ov}$ are the body, oxide and overlap of the gate thickness respectively. $L_{\rm g}$ is gate length. $N_{\rm s}$, $N_{\rm d}$ and $N_{\rm b}$ are doping concentration of source, drain and body respectively. In this work we consider $L_{\rm g}$ $=$ 45 nm, $t_{\rm ox}$ $=$ 1.9 nm, $t_{\rm ov}$ $=$ 3 nm, $t_{\rm g}$ $=$ 10 nm, $x_{\rm sd}$ $=$ 50 nm, $t_{\rm si}$ $=$ 16 nm, $N_{\rm s}$ $=$ 10$^{20}$ cm$^{-3}$

$=$

$N_{\rm d}$ and $N_{\rm b}$ $=$ 10$^{16}$ cm$^{-3}$.

DownLoad: Full-Size Img PowerPoint

Fig. 2. The equivalent circuit of the device shows that the extrinsic components can be evaluated at off condition of the device. $C_{\rm gdo}$ and $C_{\rm gso}$ are the gate to drain and the gate to source overlap capacitances respectively. $C_{\rm inner fringe}$ is the inner fringing capacitance of the device. $R_{\rm s}$ and $R_{\rm d}$ are the source and drain extrinsic parasitic resistance respectively.

DownLoad: Full-Size Img PowerPoint

Fig. 3. Extrinsic parasitic source and drain resistances ($R_{\rm s}$ and $R_{\rm d})$ extracted using the channel resistance method.

DownLoad: Full-Size Img PowerPoint

Fig. 4. The intrinsic small signal equivalent circuit of asymmetric DGMOSFET. These components can be evaluated after de-embedding the extrinsic components $C_{\rm gdo}$, $C_{\rm gso}$, $R_{\rm s}$ and $R_{\rm d}$.

DownLoad: Full-Size Img PowerPoint

Fig. 5. Small signal equivalent circuit of an asymmetric DGMOSFET for two port analysis. Asymmetric analysis contains two conditions for evaluation of intrinsic components. Condition1: Gate 2 and source grounded, i.e. $G_{y=1}$ $\ne$ 0, $D$ $\ne$ 0, $G_{z=2}$ $=$ 0 and $S$ $=$ 0. Condition 2: Gate 1 and source grounded, i.e. $G_{y=2}$ $\ne$ 0, $D$ $\ne$ 0, $G_{z=1}$ $=$ 0 and $S$ $=$ 0.

DownLoad: Full-Size Img PowerPoint

Fig. 6. The equivalent capacitance $C_{\rm gd}$ and resistance $R_{\rm gd}$ are extracted from both symmetric and asymmetric analysis. By using the superposition principle, the equivalent capacitance and resistance are evaluated from the asymmetric analysis and compared to symmetric analysis. These parameters are extracted are found to be constant with frequency.

DownLoad: Full-Size Img PowerPoint

Fig. 7. The intrinsic capacitance ($C_{\rm gd})$ and intrinsic resistance ($R_{\rm gd})$ with frequency are found to be constant. The capacitance and resistance are extracted at $V_{\rm ds}$ $=$ 0.5 V.

DownLoad: Full-Size Img PowerPoint

Fig. 8. Comparison of resistances ($R_{\rm gd})$ and capacitances ($C_{\rm gd})$ as function of gate 1 bias for different gate 2 potential, keeping the drain potential $V_{\rm ds}$ constant i.e. 0.55 V.

DownLoad: Full-Size Img PowerPoint

Fig. 9. Comparison of the capacitances ($C_{\rm gd})$ and the resistances ($R_{\rm gd})$ as a function of drain bias for different gate potentials.

DownLoad: Full-Size Img PowerPoint

Fig. 10. The time constant ($\tau_{\rm m})$ and inductance ($L_{\rm sd})$ verses frequency are extracted at $V_{\rm gs1}$ $=$ 0.6 V, $V_{\rm gs2}$ $=$ 0 V $=$ $V_{\rm s}$ and $V_{\rm ds}$ $=$ 0.55 V are found to be constant.

DownLoad: Full-Size Img PowerPoint

[1]	Suryagandh S S, Garg M, Woo J C S. A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs. IEEE Trans Electron Devices, 2004, 51(7):1122 doi: 10.1109/TED.2004.829872
[2]	Liang J, Xiao H, Huang R, et al. Design optimization of structural parameters in double gate MOSFETs for RF applications. Semicond Sci Technol, 2008, 23(5):1 doi: 10.1007/s10470-013-0164-1
[3]	Jiale L, Han X, Ru H, et al. Design optimization of structural parameters in double gate MOSFETs for RF applications. Semicond Sci Technol, 2008, 23:1 doi: 10.1007/s10470-013-0164-1
[4]	Savas K, Wei M. Optimization of RF linearity in DG-MOSFETs. IEEE Electron Device Lett, 2004, 25(5):308 doi: 10.1109/LED.2004.826539
[5]	Qiang C, Meindl J D. A comparative study of threshold variations in symmetric and asymmetric undoped double-gate MOSFETs. IEEE International SOI Conference, 2002:30 doi: 10.1007/978-3-319-01165-3_3/fulltext.html
[6]	Reddy G V, Kumar M J. Investigation of the novel attributes of a single-halo double gate SOI MOSFET:2D simulation study. Microelectron J, 2004, 35:761 doi: 10.1016/j.mejo.2004.06.003
[7]	Reddy M V R, Sharma D K, Patil M B, et al. Power-area evaluation of various double-gate RF mixer topologies. IEEE Electron Devices Lett, 2005, 26:664 doi: 10.1109/LED.2005.853632
[8]	Kaya S, Hamed H F A, Starzyk J A. Low-power tunable analog circuit blocks based on nanoscale double-gate MOSFETs. IEEE Trans Circuits Syst Ⅱ, 2007, 54(7):571 doi: 10.1109/TCSII.2007.895324
[9]	Pei G, Kan E C. Circuit design principles for independently driven double-gate MOSFETs. VLSI Tech Dig, Honolulu, HI, June 2002
[10]	Han J W, Kim C J, Choi Y K. Universal potential model in tied and separated double-gate MOSFETs with consideration of symmetric and asymmetric structure. IEEE Trans Electron Devices, 2008, 55(6):1472 doi: 10.1109/TED.2008.922492
[11]	International Technology Roadmaps for Semiconductor (ITRS). 2008
[12]	Sentaurus TCAD Manuals, Synopsys Inc. Mountain View, CA 94043, USA. Release C-2009.06; 2009
[13]	Esseni D, Mastrapasqua M, Celler G K, et al. Low field mobility of ultra-thin SOI N-and P-MOSFETs:measurements and implications on the performance of ultra-short MOSFETs. IEDM Tech Dig, 2000:671 http://www.academia.edu/27129756/Low_field_electron_and_hole_mobility_of_SOI_transistors_fabricated_on_ultrathin_silicon_films_for_deep_submicrometer_technology_application
[14]	Kang I M, Shin H. Non-quasi-static small-signal modeling and analytical parameter extraction of SOI FinFETs. IEEE Trans Nano Technol, 2006, 5(3):205 doi: 10.1109/TNANO.2006.869946
[15]	BSIM3v3.3.0 MOSFET Model-Users' Manual
[16]	Balestra F, Cristoloveanu S, Benachir M, et al. Double-gate silicon-on-insulator transistor with volume inversion:a new device with greatly enhanced performance. IEEE Electron Device Lett, 1987, 8:410 doi: 10.1109/EDL.1987.26677
[17]	Venkatesan S, Neudeck G V, Pierret R F. Double-gate operation and volume inversion in n-channel SOI MOSFET's. IEEE Electron Device Lett, 1992, 13:44 doi: 10.1109/55.144946
[18]	Balestra F. Comments on:double-gate operation and volume inversion in n-channel SOI MOSFET's. IEEE Electron Device Lett, 1992, 13:658 doi: 10.1109/55.192876
[19]	Frank D J, Laux S E, Fischetti M V. Monte Carlo simulation of a 30 nm dual-gate MOSFET:how short can Si go.Proc IEDM, San Francisco, CA, 1992:553 doi: 10.1007/s10825-009-0277-z
[20]	Omura Y, Nakashima S, Izumi K, et al. 0.1 m gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer. IEEE Trans Electron Devices, 1993, 40:1019 doi: 10.1109/16.210214
[21]	Fiegna C, Abramo A. Solution of Schrödinger and Poisson equation in single and double gate SOI MOS. Proc IEDM, San Francisco, CA, 1997:93 http://jeldev.org/16_R-Sharma.pdf

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Received: 03 December 2012 Revised: 07 January 2013 Online: Published: 01 November 2013

Article Navigation > Journal of Semiconductors > 2013 > 34(11): 114002

Sudhansu Kumar Pati, Kalyan Koley, Arka Dutta, N Mohankumar, Chandan Kumar Sarkar. A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect[J]. Journal of Semiconductors, 2013, 34(11): 114002. doi: 10.1088/1674-4926/34/11/114002 S K Pati, K Koley, A Dutta, N Mohankumar, C K Sarkar. A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect[J]. J. Semicond., 2013, 34(11): 114002. doi: 10.1088/1674-4926/34/11/114002.Export: BibTex EndNote

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S K Pati, K Koley, A Dutta, N Mohankumar, C K Sarkar. A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect[J]. J. Semicond., 2013, 34(11): 114002. doi: 10.1088/1674-4926/34/11/114002.

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A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect

doi: 10.1088/1674-4926/34/11/114002

1.
Nano Device Simulation Laboratory, Electronics and Telecommunication Engineering Department, Jadavpur University, Kolkata-700 032, India
2.
SKP college of Engineering, Tiruvannamalai, Tamilnadu-606 611, India

More Information

Corresponding author: Sudhansu Kumar Pati,Email:
Received Date: 2012-12-03
Revised Date: 2013-01-07

Published Date: 2013-11-01

Abstract

Abstract

In analog circuit design an important parameter, from the perspective of superior device performance, is linearity. The DG MOSFET in asymmetric mode operation has been found to present a better linearity. In addition to that it provides, at the discretion of analog circuit designer, an additional degree of freedom, by providing independent bias control for the front and the back gates. Here a non-quasi-static (NQS) small signal model for DGMOSFET with asymmetric gate bias is proposed for extracting the parameters of the device using TCAD simulations. The parameters extracted here for analysis are the intrinsic front and back gate to drain capacitance, C_gd1 and C_gd2, the intrinsic front and back distributed channel resistance, R_gd1 and R_gd2 respectively, the transport delay, τ_m, and the inductance, L_sd. The parameter extraction model for an asymmetric DG MOSFET is validated with pre-established extracted parameter data, for symmetric DG MOSFET devices, from the available literature. The device simulation is performed with respect to frequency up to 100 GHz.
- asymmetric DGMOSFET,
- RF modeling,
- small signal analysis,
- parameter extraction

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References(21)

References

[1]	Suryagandh S S, Garg M, Woo J C S. A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs. IEEE Trans Electron Devices, 2004, 51(7):1122 doi: 10.1109/TED.2004.829872
[2]	Liang J, Xiao H, Huang R, et al. Design optimization of structural parameters in double gate MOSFETs for RF applications. Semicond Sci Technol, 2008, 23(5):1 doi: 10.1007/s10470-013-0164-1
[3]	Jiale L, Han X, Ru H, et al. Design optimization of structural parameters in double gate MOSFETs for RF applications. Semicond Sci Technol, 2008, 23:1 doi: 10.1007/s10470-013-0164-1
[4]	Savas K, Wei M. Optimization of RF linearity in DG-MOSFETs. IEEE Electron Device Lett, 2004, 25(5):308 doi: 10.1109/LED.2004.826539
[5]	Qiang C, Meindl J D. A comparative study of threshold variations in symmetric and asymmetric undoped double-gate MOSFETs. IEEE International SOI Conference, 2002:30 doi: 10.1007/978-3-319-01165-3_3/fulltext.html
[6]	Reddy G V, Kumar M J. Investigation of the novel attributes of a single-halo double gate SOI MOSFET:2D simulation study. Microelectron J, 2004, 35:761 doi: 10.1016/j.mejo.2004.06.003
[7]	Reddy M V R, Sharma D K, Patil M B, et al. Power-area evaluation of various double-gate RF mixer topologies. IEEE Electron Devices Lett, 2005, 26:664 doi: 10.1109/LED.2005.853632
[8]	Kaya S, Hamed H F A, Starzyk J A. Low-power tunable analog circuit blocks based on nanoscale double-gate MOSFETs. IEEE Trans Circuits Syst Ⅱ, 2007, 54(7):571 doi: 10.1109/TCSII.2007.895324
[9]	Pei G, Kan E C. Circuit design principles for independently driven double-gate MOSFETs. VLSI Tech Dig, Honolulu, HI, June 2002
[10]	Han J W, Kim C J, Choi Y K. Universal potential model in tied and separated double-gate MOSFETs with consideration of symmetric and asymmetric structure. IEEE Trans Electron Devices, 2008, 55(6):1472 doi: 10.1109/TED.2008.922492
[11]	International Technology Roadmaps for Semiconductor (ITRS). 2008
[12]	Sentaurus TCAD Manuals, Synopsys Inc. Mountain View, CA 94043, USA. Release C-2009.06; 2009
[13]	Esseni D, Mastrapasqua M, Celler G K, et al. Low field mobility of ultra-thin SOI N-and P-MOSFETs:measurements and implications on the performance of ultra-short MOSFETs. IEDM Tech Dig, 2000:671 http://www.academia.edu/27129756/Low_field_electron_and_hole_mobility_of_SOI_transistors_fabricated_on_ultrathin_silicon_films_for_deep_submicrometer_technology_application
[14]	Kang I M, Shin H. Non-quasi-static small-signal modeling and analytical parameter extraction of SOI FinFETs. IEEE Trans Nano Technol, 2006, 5(3):205 doi: 10.1109/TNANO.2006.869946
[15]	BSIM3v3.3.0 MOSFET Model-Users' Manual
[16]	Balestra F, Cristoloveanu S, Benachir M, et al. Double-gate silicon-on-insulator transistor with volume inversion:a new device with greatly enhanced performance. IEEE Electron Device Lett, 1987, 8:410 doi: 10.1109/EDL.1987.26677
[17]	Venkatesan S, Neudeck G V, Pierret R F. Double-gate operation and volume inversion in n-channel SOI MOSFET's. IEEE Electron Device Lett, 1992, 13:44 doi: 10.1109/55.144946
[18]	Balestra F. Comments on:double-gate operation and volume inversion in n-channel SOI MOSFET's. IEEE Electron Device Lett, 1992, 13:658 doi: 10.1109/55.192876
[19]	Frank D J, Laux S E, Fischetti M V. Monte Carlo simulation of a 30 nm dual-gate MOSFET:how short can Si go.Proc IEDM, San Francisco, CA, 1992:553 doi: 10.1007/s10825-009-0277-z
[20]	Omura Y, Nakashima S, Izumi K, et al. 0.1 m gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer. IEEE Trans Electron Devices, 1993, 40:1019 doi: 10.1109/16.210214
[21]	Fiegna C, Abramo A. Solution of Schrödinger and Poisson equation in single and double gate SOI MOS. Proc IEDM, San Francisco, CA, 1997:93 http://jeldev.org/16_R-Sharma.pdf

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