SEMICONDUCTOR DEVICES

Simulation study on short channel double-gate junctionless field-effect transistors

Meile Wu1, Xiaoshi Jin1, , Rongyan Chuai1, Xi Liu1 and Jong-Ho Lee2

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 Corresponding author: Jin Xiaoshi, Email:xsjin@live.cn

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Abstract: We study the characteristics of short channel double-gate (DG) junctionless (JL) FETs by device simulation. Output Ⅰ-Ⅴ characteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed. Distributions of electron concentration, electric field and potential in the body channel region are also analyzed. Comparisons with conventional inversion-mode (IM) FETs, which can demonstrate the advantages of JL FETs, have also been performed.

Key words: short channel effectdouble-gatejunctionless field-effect transistordevice simulation



[1]
Duarte J P, Kim M S, Choi S J, et al. A compact model of quantum electron density at the subthreshold region for double-gate junctionless transistor. IEEE Trans Electron Devices, 2012, 59(4):1008 doi: 10.1109/TED.2012.2185827
[2]
Jin X, Liu X, Lee J, et al. A continuous current model of fully-depleted symmetric double-gate MOSFETs considering a wide range of body doping concentrations. Semicond Sci Technol, 2010, 25(5):055018 doi: 10.1088/0268-1242/25/5/055018
[3]
Diagne B, Prégaldiny F, Lallement C, et al. Explicit compact model for symmetric double-gate MOSFETs including solutions for small-geometry effects. Solid-State Electron, 2008, 52(1):99 doi: 10.1016/j.sse.2007.06.020
[4]
Colinge J P, Lee C W, Afzalian A, et al. Nanowire transistors without junctions. Nat Nanotechnology, 2010, 5(3):225 doi: 10.1038/nnano.2010.15
[5]
Gnani E, Gnudi A, Reggiani S, et al. Theory of the junctionless nanowire FET. IEEE Trans Electron Devices, 2011, 58(9):2903 doi: 10.1109/TED.2011.2159608
[6]
Gnani E, Gnudi A, Reggiani S, et al. Numerical investigation on the junctionless nanowire FET. Solid-State Electron, 2012, 71:13 doi: 10.1016/j.sse.2011.10.013
[7]
Colinge J P, Ferain I, Kranti A, et al. Junctionless nanowire transistor:complementary metal-oxide-semiconductor without junctions. Sci Adv Mater, 2011, 3(3):477 doi: 10.1166/sam.2011.1163
[8]
SILVACO International. ATLAS User's Manual, 2005
[9]
Shoji M, Horiguchi S. Electronic structures and phonon limited electron mobility of double-gate silicon-on insulator Si inversion layers. J Appl Phys, 1999, 85:2722 doi: 10.1063/1.369589
Fig. 1.  2D schematic view of a DG JL FET. The S/D region and body region of the JL FET have the same doping type and concentration. $L$ is the channel length; $t_{\rm b}$ and $t_{\rm ox}$ are respectively the thicknesses of the silicon body and the gate oxide.

Fig. 2.  (a) Turn-on characteristics of the DG JL FET with $V_{\rm DS}$ $=$ 1 V. (b) Output characteristics of the DG JL FET for $V_{\rm GS}$ ranging between 0.5 and 1.3 V in steps of 0.2 V. The device parameters are $L$ $=$ 30 nm, $W$ $=$ 10 nm, $t_{\rm b}$ $=$ 10 nm, $N_{\rm D}$ $=$ 1 $\times$ 10$^{18}$ cm$^{-3}$. (c) Comparison of turn-on characteristics between DG JL FET and DG IM FETs. We regulate the conventional MOSFET's threshold voltage, making it equal to the $V_{\rm T}$ of the DG JL FETs. The two curves are similar. (d) Comparison of the distribution of electron concentration between the two devices above with the same $V_{\rm GS}$ ($V_{\rm GS}$ $=$ 0.2 V) and $V_{\rm DS}$ ($V_{\rm DS}$ $=$ 0.05) in the perpendicular direction of channel at the point of $L$/2. The parameters of both devices are $L$ $=$ 50 nm, $W$ $=$ 10 nm, $t_{\rm b}$ $=$ 10 nm and $N_{\rm D}$ $=$ $N_{\rm A}$ $=$ 5 $\times$ 10$^{18}$ cm$^{-3}$.

Fig. 3.  Impact of channel length of junctionless and conventional devices. (a) Comparison of the turn-on characteristics of junctionless and conventional devices. The two devices parameters are $W$ $=$ 10 nm, $t_{\rm b}$ $=$ 10 nm and $N_{\rm D}$ $=$ $N_{\rm A}$ $=$ 2 $\times$ 10$^{18}$ cm$^{-3}$, and the changes of the channel length are both set to 10 nm, 20 nm, 30 nm and 1 $\mu$m. The $V_{\rm DS}$ is set to 1 V. (b) Turn-on characteristics of the two devices for $V_{\rm DS}$ $=$ 0.05 V. In the both of the two situations above, the threshold voltages of the two devices decrease with the diminution of the channel lengths and the change of junctionless DG MOSFETs is smaller than conventional DG MOSFETs. (c) Curve of $\Delta V_{\rm T}$-channel length. Calculate the difference between the threshold voltage with $L$ $=$ 1 $\mu$m and the threshold voltage with $L$ $=$ 10 nm, 20 nm, 30 nm of junctionless and conventional DG MOSFETs, respectively. (d) Influence of channel length on SS. Change the $L$ of the two kinds of devices to 10 nm, 20 nm and 30 nm. SS increases with the decrease of $L$ and the influence on SS of $L$ of DG JL FET is smaller than DG IM FET.

Fig. 4.  (a) Influence of the doping concentration on DG JL FETs. The parameters of the DG JL FET are $L$ $=$ 30 nm, $W$ $=$ 10 nm, $t_{\rm b}$ $=$ 10 nm. Change the doping concentration of nanowire respectively to 1 $\times$ 10$^{14}$ cm$^{-3}$, 5 $\times$ 10$^{17}$ cm$^{-3}$, 1 $\times$ 10$^{18}$ cm$^{-3}$, 5 $\times$ 10$^{18}$ cm$^{-3}$, 1 $\times$ 10$^{19}$ cm$^{-3}$ and 2 $\times$ 10$^{19}$ cm$^{-3}$, then compare their turn-on characteristics for $V_{\rm DS}$ $=$ 0.05 V. The $V_{\rm T}$ decreases with the addition of doping concentration of channel. When the doping concentration exceeds a certain value, the device $V_{\rm T}$ is negative. The change of $V_{\rm T}$ is not obvious at lower doping concentration. (b) Curve of $\Delta V_{\rm T}$-channel length of the DG JL FET. Calculate the difference between the threshold voltage with $N_{\rm D}$ $=$ 1 $\times$ 10$^{17}$ cm$^{-3}$ and the threshold voltage with $N_{\rm D}$ $=$ 1 $\times$ 10$^{17}$ cm$^{-3}$, 2 $\times$ 10$^{17}$ cm$^{-3}$, 3 $\times$ 10$^{17}$ cm$^{-3}$, 5 $\times$ 10$^{17}$ cm$^{-3}$, 8 $\times$ 10$^{17}$ cm$^{-3}$, 1 $\times$ 10$^{18}$ cm$^{-3}$, 2 $\times$ 10$^{18}$ cm$^{-3}$, 3 $\times$ 10$^{18}$ cm$^{-3}$ and 5 $\times$ 10$^{18}$ cm$^{-3}$ of DG JL MOSFETs respectively. (c) Changes of $V_{\rm T}$ with doping concentration of DG JL FETs and traditional DG MOSFETs. The parameters of the both devices are $L$ $=$ 30 nm, $W$ $=$ 10 nm, $t_{\rm b}$ $=$ 10 nm. Change $N_{\rm D}$ and $N_{\rm A}$ to 1 $\times$ 10$^{17}$ cm$^{-3}$, 1 $\times$ 10$^{18}$ cm$^{-3}$, 5 $\times$ 10$^{18}$ cm$^{-3}$ and 1 $\times$ 10$^{19}$ cm$^{-3}$. The JL FET $V_{\rm T}$ decreases with the augment of nanowire doping concentration of the JL FET, while the traditional MOSFET $V_{\rm T}$ increases instead.

Fig. 5.  (a) Influence of body thickness for DG JL FETs. Set the body thickness of the DG JL FET whose parameters are $L$ $=$ 30 nm, $W$ $=$ 10 nm, $N_{\rm D}$ $=$ 1 $\times$ 10$^{18}$ cm$^{-3}$ to 5, 10, 15 and 20 nm. The $V_{\rm T}$ decreases with the addition of $t_{\rm b}$. The SSs of the above four devices are 63, 72, 94, and 128 mV/dec separately. SS increases gradually with the increase of the body thickness. (b) Comparison of the turn-on characteristics of JL FETs with different channel lengths under the same situation of the ratio of body thickness to channel length. For two DG JL FETs with $L$ $=$ 10 nm, $L$ $=$ 15 nm and $L$ $=$ 20 nm, when their $t_{\rm b}$/$L$ $=$ 1, their threshold voltages are very similar.

Fig. 6.  Distribution of electron concentration and electrostatic potential in the channel direction with different $t_{\rm b}$. Set the DG JL FETs' parameters as $L$ $=$ 20 nm, $W$ $=$ 10 nm, $N_{\rm D}$ $=$ 1 $\times$ 10$^{18}$ cm$^{-3}$, and different $t_{\rm b}$ as 10 nm, 20 nm and 40 nm, $V_{\rm GS}$ $=$ $-0.2$ V, $V_{\rm DS}$ $=$ 0.5 V. (a) The distribution of electron concentration with different $t_{\rm b}$ in the direction of channel at the point of 1 nm far from the surface of silicon body. (b) The distribution of electrostatic potential. The electron concentration and the potential increased with the increasing of $t_{\rm b}$.

Fig. 7.  Distribution of electron concentration, electric field and electric potential in the perpendicular channel direction. Set $V_{\rm DS}$ to 0.5 V and change the gate voltage ($-0.8$, $-0.4$, 0, 0.4, 0.8 V). (a) Comparison of the distribution of electron concentration in the perpendicular channel direction in different situations. (b) Distribution of electrostatic potential. (c) Distribution of electric field. (d) Partial enlargement of the electric field.

Fig. 8.  (a) Turn-on characteristics in log of the DG JL FET for different $V_{\rm DS}$ (0.2, 0.4, 0.6, 0.8, 1.0, 1.2 V). (b) Turn-on characteristics in linear scales. (c) Distribution of electrostatic potential in the channel direction of the DG JL FET for $V_{\rm DS}$ ranging from 0.2 to 1.2 V in steps of 0.2 V and $V_{\rm DS}$ $=$ 1.5 V at the point of $t_{\rm b}$/2. (d) Distribution of electrostatic potential in the perpendicular channel direction at the point of $L$/2. The electrostatic potential increases with the increasing $V_{\rm DS}$. (e) Curve of SS-$V_{\rm DS}$ of the two devices. SSs of both kinds of devices increase with the increase of $V_{\rm DS}$. The influence on SS of DG JL FET of $V_{\rm DS}$ is smaller than that for DG IM FET.

[1]
Duarte J P, Kim M S, Choi S J, et al. A compact model of quantum electron density at the subthreshold region for double-gate junctionless transistor. IEEE Trans Electron Devices, 2012, 59(4):1008 doi: 10.1109/TED.2012.2185827
[2]
Jin X, Liu X, Lee J, et al. A continuous current model of fully-depleted symmetric double-gate MOSFETs considering a wide range of body doping concentrations. Semicond Sci Technol, 2010, 25(5):055018 doi: 10.1088/0268-1242/25/5/055018
[3]
Diagne B, Prégaldiny F, Lallement C, et al. Explicit compact model for symmetric double-gate MOSFETs including solutions for small-geometry effects. Solid-State Electron, 2008, 52(1):99 doi: 10.1016/j.sse.2007.06.020
[4]
Colinge J P, Lee C W, Afzalian A, et al. Nanowire transistors without junctions. Nat Nanotechnology, 2010, 5(3):225 doi: 10.1038/nnano.2010.15
[5]
Gnani E, Gnudi A, Reggiani S, et al. Theory of the junctionless nanowire FET. IEEE Trans Electron Devices, 2011, 58(9):2903 doi: 10.1109/TED.2011.2159608
[6]
Gnani E, Gnudi A, Reggiani S, et al. Numerical investigation on the junctionless nanowire FET. Solid-State Electron, 2012, 71:13 doi: 10.1016/j.sse.2011.10.013
[7]
Colinge J P, Ferain I, Kranti A, et al. Junctionless nanowire transistor:complementary metal-oxide-semiconductor without junctions. Sci Adv Mater, 2011, 3(3):477 doi: 10.1166/sam.2011.1163
[8]
SILVACO International. ATLAS User's Manual, 2005
[9]
Shoji M, Horiguchi S. Electronic structures and phonon limited electron mobility of double-gate silicon-on insulator Si inversion layers. J Appl Phys, 1999, 85:2722 doi: 10.1063/1.369589
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    Received: 25 July 2012 Revised: 12 September 2012 Online: Published: 01 March 2013

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      Meile Wu, Xiaoshi Jin, Rongyan Chuai, Xi Liu, Jong-Ho Lee. Simulation study on short channel double-gate junctionless field-effect transistors[J]. Journal of Semiconductors, 2013, 34(3): 034004. doi: 10.1088/1674-4926/34/3/034004 M L Wu, X S Jin, R Y Chuai, X Liu, J H Lee. Simulation study on short channel double-gate junctionless field-effect transistors[J]. J. Semicond., 2013, 34(3): 034004. doi:  10.1088/1674-4926/34/3/034004.Export: BibTex EndNote
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      Meile Wu, Xiaoshi Jin, Rongyan Chuai, Xi Liu, Jong-Ho Lee. Simulation study on short channel double-gate junctionless field-effect transistors[J]. Journal of Semiconductors, 2013, 34(3): 034004. doi: 10.1088/1674-4926/34/3/034004

      M L Wu, X S Jin, R Y Chuai, X Liu, J H Lee. Simulation study on short channel double-gate junctionless field-effect transistors[J]. J. Semicond., 2013, 34(3): 034004. doi:  10.1088/1674-4926/34/3/034004.
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      Simulation study on short channel double-gate junctionless field-effect transistors

      doi: 10.1088/1674-4926/34/3/034004
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      Project supported by the Fund of Liaoning Province Education Department (No. L2012028)

      the Fund of Liaoning Province Education Department L2012028

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      • Corresponding author: Jin Xiaoshi, Email:xsjin@live.cn
      • Received Date: 2012-07-25
      • Revised Date: 2012-09-12
      • Published Date: 2013-03-01

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