J. Semicond. > 2013, Volume 34 > Issue 4 > 045007, doi: 10.1088/1674-4926/34/4/045007
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SEMICONDUCTOR INTEGRATED CIRCUITS

A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration

Yingying Chi1, and Dongmei Li2

+ Author Affiliations

 Corresponding author: Chi Yingying, Email:xingye_314529@126.com

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Abstract: A power efficient 96.1 dB-SFDR successive approximation register (SAR) analog-to-digital converter (ADC) with digital calibration aimed at capacitor mismatch is presented. The prototype is fabricated in a 0.18 μm CMOS. The charge redistribution (CR) design and an extra ΔΣ modulator for capacitance measurement are employed. With a 1.1 MS/s sampling rate, the ADC achieves 70.8 dB SNDR and the power consumption is 2.1 mW.

Key words: successive approximation register, ADC, low power, calibration



[1]
Sun L, Dai Q, Lee C, et al. Analysis on capacitor mismatch and parasitic capacitors effect of improved segmented-capacitor array in SAR ADC. ⅡTA Third International Symposium on Intelligent Information Technology Application, 2009, 2:280 http://ieeexplore.ieee.org/document/5369251/authors
[2]
Liu Liyuan, Li Dongmei, Chen Liangdong, et al. A low power 8-bit successive approximation register (SAR) A/D for wireless body sensor node (WBSN). Journal of Semiconductors, 2010, 31(6):065004 doi: 10.1088/1674-4926/31/6/065004
[3]
Aksin D, Al-Shyoukh M A, Maloberti F. A bootstrapped switch for precise sampling of inputs with signal range beyond supply voltage. IEEE Custom Integrated Circuits Conference, 2005:743 http://dblp.uni-trier.de/db/conf/cicc/cicc2005.html
[4]
Liu Liyuan, Chen Liangdong, Li Dongmei, et al. A 1.1 mW 87 dB dynamic range ΔΣ modulator for audio applications. Journal of Semiconductors, 2010, 31(5):055003 doi: 10.1088/1674-4926/31/5/055003
[5]
Schinkel D, Mensink E, Klumperink E, et al. A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time. IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2007 http://ieeexplore.ieee.org/document/4242391/keywords
[6]
Baird R T, Fiez T S. Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging. IEEE Trans Circuits Syst Ⅱ, 1995, 42(12):753 doi: 10.1109/82.476173
Fig. 1.  Performance of the SAR ADC.

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Fig. 2.  Block diagram of the circuit design.

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Fig. 3.  Design of the DAC with a split-capacitor array.

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Fig. 4.  Main control logic block and the timing diagram of the SAR.

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Fig. 5.  Design of the DSM.

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Fig. 6.  Main structure of the OTA with bias and common-mode feedback.

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Fig. 7.  Comparator of quantizer proposed in Ref. [5].

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Fig. 8.  Die photograph of the chip.

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Fig. 9.  Measurement of the SNDR with varying input.

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Fig. 10.  Spectrum contrast before and after calibration.

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Table 1.   Performance summary.
[1]
Sun L, Dai Q, Lee C, et al. Analysis on capacitor mismatch and parasitic capacitors effect of improved segmented-capacitor array in SAR ADC. ⅡTA Third International Symposium on Intelligent Information Technology Application, 2009, 2:280 http://ieeexplore.ieee.org/document/5369251/authors
[2]
Liu Liyuan, Li Dongmei, Chen Liangdong, et al. A low power 8-bit successive approximation register (SAR) A/D for wireless body sensor node (WBSN). Journal of Semiconductors, 2010, 31(6):065004 doi: 10.1088/1674-4926/31/6/065004
[3]
Aksin D, Al-Shyoukh M A, Maloberti F. A bootstrapped switch for precise sampling of inputs with signal range beyond supply voltage. IEEE Custom Integrated Circuits Conference, 2005:743 http://dblp.uni-trier.de/db/conf/cicc/cicc2005.html
[4]
Liu Liyuan, Chen Liangdong, Li Dongmei, et al. A 1.1 mW 87 dB dynamic range ΔΣ modulator for audio applications. Journal of Semiconductors, 2010, 31(5):055003 doi: 10.1088/1674-4926/31/5/055003
[5]
Schinkel D, Mensink E, Klumperink E, et al. A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time. IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2007 http://ieeexplore.ieee.org/document/4242391/keywords
[6]
Baird R T, Fiez T S. Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging. IEEE Trans Circuits Syst Ⅱ, 1995, 42(12):753 doi: 10.1109/82.476173

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    Received: 14 September 2012 Revised: 09 October 2012 Online: Published: 01 April 2013

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      Article Navigation >  Journal of Semiconductors  > 2013  >  34(4): 045007
      Yingying Chi, Dongmei Li. A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration[J]. Journal of Semiconductors, 2013, 34(4): 045007. doi: 10.1088/1674-4926/34/4/045007 Y Y Chi, D M Li. A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration[J]. J. Semicond., 2013, 34(4): 045007. doi: 10.1088/1674-4926/34/4/045007.Export: BibTex EndNote
      Citation:
      Yingying Chi, Dongmei Li. A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration[J]. Journal of Semiconductors, 2013, 34(4): 045007. doi: 10.1088/1674-4926/34/4/045007

      Y Y Chi, D M Li. A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration[J]. J. Semicond., 2013, 34(4): 045007. doi: 10.1088/1674-4926/34/4/045007.
      Export: BibTex EndNote
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      A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration

      doi: 10.1088/1674-4926/34/4/045007
      • 1.

        Institution of Microelectronics of Tsinghua University, Beijing 100084, China

      • 2.

        Department of Electronic Engineering, Tsinghua University, Beijing 100084, China

      More Information
      • Corresponding author: Chi Yingying, Email:xingye_314529@126.com
      • Received Date: 2012-09-14
      • Revised Date: 2012-10-09
      • Published Date: 2013-04-01

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