SEMICONDUCTOR INTEGRATED CIRCUITS

SRAM standby leakage decoupling analysis for different leakage reduction techniques

Qing Dong and Yinyin Lin

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 Corresponding author: Lin Yinyin, Email:yylin@fudan.edu.cn

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Abstract: SRAM standby leakage reduction plays a pivotal role in minimizing the power consumption of application processors. Generally, four kinds of techniques are often utilized for SRAM standby leakage reduction:Vdd lowering (VDDL), Vss rising (VSSR), BL floating (BLF) and reversing body bias (RBB). In this paper, we comprehensively analyze and compare the reduction effects of these techniques on different kinds of leakage. It is disclosed that the performance of these techniques depends on the leakage composition of the SRAM cell and temperature. This has been verified on a 65 nm SRAM test macro.

Key words: SRAMstandby powerleakage reduction



[1]
Lee Y, Seok M, Hanson S, et al. Standby power reduction techniques for ultra-low power processors. IEEE ESSCIRC, 2008:186 http://web.eecs.umich.edu/faculty/blaauw/images/pdfs/366.pdf
[2]
Kumar A, Qin H, Ishwar P, et al. Fundamental bounds on power reduction during data-retention in standby SRAM. IEEE International Symposium on Circuits and System, 2007:1867 http://ieeexplore.ieee.org/document/4253026/authors
[3]
Hamzaoglu F, Zhang K, Wang Y, et al. A 3.8 GHz 153 Mb SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high-k metal gate CMOS technology. IEEE J Solid-State Circuits, 2009, 44(1):148 doi: 10.1109/JSSC.2008.2007151
[4]
Lai F, Lee C. On-chip voltage down converter to improve SRAM read/write margin and static power for sub-nano CMOS technology. IEEE J Solid-State Circuits, 2007, 42(9):2061 doi: 10.1109/JSSC.2007.903072
[5]
Wang Y, Bhattacharya U, Hamzaoglu F, et al. A 4.0 GHz 291 Mb voltage-scalable SRAM design in a 32 nm high-k + metal-gate CMOS technology with integrated power management. IEEE J Solid-State Circuits, 2010, 45(1):103 doi: 10.1109/JSSC.2009.2034082
[6]
Yamaoka M, Kawahara T. Operating-margin-improved SRAM with column-at-a-time body-bias control technique. IEEE ESSCIRC Dig, 2007:396
[7]
Yamaoka M, Shinozaki Y, Maeda N, et al. A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. IEEE J Solid-State Circuits, 2005, 40(1):186 doi: 10.1109/JSSC.2004.838014
[8]
Lakshminarayanan S, Joung J, Narasimhan G, et al. Standby power reduction and SRAM cell optimization for 65 nm technology. IEEE International Symposium on Quality Electronic Design, 2009:471
[9]
Maeda N, Komatsu S, Morimoto M, et al. A 0.41μA standby leakage 32 kb embedded SRAM with low-voltage resume-standby utilizing all digital current comparator in 28 nm HKMG CMOS. IEEE VLSI Circuits Symp Dig, 2012:58
[10]
Hsu P K, Tang Y, Tao D, et al. A SRAM cell array with adaptive leakage reduction scheme for data retention in 28 nm high-k metal-gate CMOS. IEEE VLSI Circuits Symp Dig, 2012:62 https://www.infona.pl/resource/bwmeta1.element.ieee-art-000006243790
Fig. 1.  All standby leakage paths in the SRAM cell.

Fig. 2.  The relationship between temperature and each type of leakage currents.

Fig. 3.  (Color online) Leakage composition under different temperatures.

Fig. 4.  (Color online) Leakage reduction effects of the VDDL.

Fig. 5.  (Color online) Leakage reduction effects of the VSSR.

Fig. 6.  (Color online) Leakage reduction effects of the BLF.

Fig. 7.  (Color online) Leakage reduction effects of the NW RBB.

Fig. 8.  (Color online) Leakage reduction effects of the PW RBB.

Fig. 9.  Schematic diagram of a SRAM test macro.

Fig. 10.  Die photo of SRAM test macro.

Fig. 11.  Measured results of leakage reduction techniques.

[1]
Lee Y, Seok M, Hanson S, et al. Standby power reduction techniques for ultra-low power processors. IEEE ESSCIRC, 2008:186 http://web.eecs.umich.edu/faculty/blaauw/images/pdfs/366.pdf
[2]
Kumar A, Qin H, Ishwar P, et al. Fundamental bounds on power reduction during data-retention in standby SRAM. IEEE International Symposium on Circuits and System, 2007:1867 http://ieeexplore.ieee.org/document/4253026/authors
[3]
Hamzaoglu F, Zhang K, Wang Y, et al. A 3.8 GHz 153 Mb SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high-k metal gate CMOS technology. IEEE J Solid-State Circuits, 2009, 44(1):148 doi: 10.1109/JSSC.2008.2007151
[4]
Lai F, Lee C. On-chip voltage down converter to improve SRAM read/write margin and static power for sub-nano CMOS technology. IEEE J Solid-State Circuits, 2007, 42(9):2061 doi: 10.1109/JSSC.2007.903072
[5]
Wang Y, Bhattacharya U, Hamzaoglu F, et al. A 4.0 GHz 291 Mb voltage-scalable SRAM design in a 32 nm high-k + metal-gate CMOS technology with integrated power management. IEEE J Solid-State Circuits, 2010, 45(1):103 doi: 10.1109/JSSC.2009.2034082
[6]
Yamaoka M, Kawahara T. Operating-margin-improved SRAM with column-at-a-time body-bias control technique. IEEE ESSCIRC Dig, 2007:396
[7]
Yamaoka M, Shinozaki Y, Maeda N, et al. A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. IEEE J Solid-State Circuits, 2005, 40(1):186 doi: 10.1109/JSSC.2004.838014
[8]
Lakshminarayanan S, Joung J, Narasimhan G, et al. Standby power reduction and SRAM cell optimization for 65 nm technology. IEEE International Symposium on Quality Electronic Design, 2009:471
[9]
Maeda N, Komatsu S, Morimoto M, et al. A 0.41μA standby leakage 32 kb embedded SRAM with low-voltage resume-standby utilizing all digital current comparator in 28 nm HKMG CMOS. IEEE VLSI Circuits Symp Dig, 2012:58
[10]
Hsu P K, Tang Y, Tao D, et al. A SRAM cell array with adaptive leakage reduction scheme for data retention in 28 nm high-k metal-gate CMOS. IEEE VLSI Circuits Symp Dig, 2012:62 https://www.infona.pl/resource/bwmeta1.element.ieee-art-000006243790
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    Received: 15 August 2012 Revised: 05 November 2012 Online: Published: 01 April 2013

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      Qing Dong, Yinyin Lin. SRAM standby leakage decoupling analysis for different leakage reduction techniques[J]. Journal of Semiconductors, 2013, 34(4): 045008. doi: 10.1088/1674-4926/34/4/045008 Q Dong, Y Y Lin. SRAM standby leakage decoupling analysis for different leakage reduction techniques[J]. J. Semicond., 2013, 34(4): 045008. doi: 10.1088/1674-4926/34/4/045008.Export: BibTex EndNote
      Citation:
      Qing Dong, Yinyin Lin. SRAM standby leakage decoupling analysis for different leakage reduction techniques[J]. Journal of Semiconductors, 2013, 34(4): 045008. doi: 10.1088/1674-4926/34/4/045008

      Q Dong, Y Y Lin. SRAM standby leakage decoupling analysis for different leakage reduction techniques[J]. J. Semicond., 2013, 34(4): 045008. doi: 10.1088/1674-4926/34/4/045008.
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      SRAM standby leakage decoupling analysis for different leakage reduction techniques

      doi: 10.1088/1674-4926/34/4/045008
      Funds:

      the National High Technology Research and Development Program of China 2011AA010404

      the National High Technology Research and Development Program of China 2008AA031401

      the Shanghai STC Project 12XD1400800

      the National ST Project 2011ZX02502

      Project supported by the National High Technology Research and Development Program of China (Nos. 2008AA031401, 2011AA010404), the National ST Project (No. 2011ZX02502), and the Shanghai STC Project (No. 12XD1400800)

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      • Corresponding author: Lin Yinyin, Email:yylin@fudan.edu.cn
      • Received Date: 2012-08-15
      • Revised Date: 2012-11-05
      • Published Date: 2013-04-01

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