SEMICONDUCTOR INTEGRATED CIRCUITS

A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling

Zhenhai Chen1, 2, , Hongwen Qian2, Songren Huang1, 2, Hong Zhang3 and Zongguang Yu1, 2

+ Author Affiliations

 Corresponding author: Chen Zhenhai, Email:diaoyuds@126.com

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Abstract: A 10-bit 250-MSPS two-channel time-interleaved charge-domain (CD) pipelined analog-to-digital converter (ADC) is presented. MOS bucket-brigade device (BBD) based CD pipelined architecture is used to achieve low power consumption. An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter. A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability. The ADC achieves a spurious free dynamic range (SFDR) of 67.1 dB, signal-to-noise ratio (SNDR) of 55.1 dB for a 10.1 MHz input, and SFDR of 61.6 dB, SNDR of 52.6 dB for a 355 MHz input at full sampling rate. Differential nonlinearity (DNL) is +0.5/-0.4 LSB and integral nonlinearity (INL) is +0.8/-0.75 LSB. Fabricated in a 0.18-μm 1P6M CMOS process, the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area, and consumes only 68 mW at 1.8 V supply.

Key words: time-interleavedpipelined analog-to-digital convertercharge domainlow powerbootstrapped sampling switchdelay locked loop



[1]
Black W C, Hodges D A. Time interleaved converter arrays. IEEE J Solid-State Circuits, 1980, 15(6):1022 doi: 10.1109/JSSC.1980.1051512
[2]
Arias J, Boccuzzi V, Quintanilla L, et al. Low-power pipeline ADC for wireless LANs. IEEE J Solid-State Circuits, 2004, 39(8):1338 doi: 10.1109/JSSC.2004.831477
[3]
Min B M, Kim P, Bowman F W, et al. A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC. IEEE J Solid-State Circuits, 2003, 38(12):2031 doi: 10.1109/JSSC.2003.819166
[4]
Hsu C C, Huang F C, Shih C Y, et al. An 11 b 800 MS/s time-interleaved ADC with digital background calibration. IEEE ISSCC Dig Tech Papers, 2007:464 https://rd.springer.com/content/pdf/bbm%3A978-90-481-9716-3%2F1.pdf
[5]
Law C H, Hurst P J, Lewis S H. A four-channel time-interleaved ADC with digital calibration of inter-channel timing and memory errors. IEEE J Solid-State Circuits, 2010, 45(10):2091 doi: 10.1109/JSSC.2010.2061630
[6]
Buchanan J E. Bucket brigade analog-to-digital converter. US Patent, No. 4072938, 1978
[7]
Anthony M, Kohler E, Kurtze J, et al. A process-scalable low-power charge-domain 13-bit pipeline ADC. Symposium on VLSI Circuits, 2008:222 doi: 10.1007/978-90-481-3083-2_3/fulltext.html
[8]
Anthony M, Kurtze J. Charge domain pipelined analog to digital converter. US Patent, No. 7570192, 2009
[9]
Chen Z H, Yu Z G, Huang S R. et al. A PVT insensitive boosted charge transfer for high speed charge-domain pipelined ADCs. IEICE Electron Express, 2012, 9(6):565 doi: 10.1587/elex.9.565
[10]
Liang C K, Yang R J, Liu S I. An all-digital fast-locking programmable DLL-based clock generator. IEEE Trans Circuits Syst I:Regular Papers, 2008, 55(1):361 doi: 10.1109/TCSI.2007.913612
[11]
Abo A M, Gray P R. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J Solid-State Circuits, 1999, 34(5):599 doi: 10.1109/4.760369
[12]
Hu X Y, Zhou Y M. A CMOS sampling switch for 14 bit 50 MHz pipelined A/D converter. Chinese Journal of Semiconductors, 2007, 28(9):1808
[13]
Aksin D, Al-Shyoukh M, Maloberti F. Switch bootstrapping for precise sampling beyond supply voltage. IEEE J Solid-State Circuits, 2006, 41(8):1938 doi: 10.1109/JSSC.2006.875305
[14]
Xu Lai, Yin Xiumei, Yang Huazhong. A 10-bit 100 Msps low power time-interleaved ADC using OTA sharing. Journal of Semiconductors, 2010, 31(9):095012 doi: 10.1088/1674-4926/31/9/095012
[15]
Chu J, Lee H S. A 450 MS/s 10-bit time-interleaved zero-crossing based ADC. IEEE Custom Integrated Circuits Conference, 2011:1 doi: 10.1007/s10470-014-0299-8
[16]
Kim Y H, Lee J, Cho S H. A 10-bit 300 MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages. IEEE International Symposium on Circuits and Systems, 2010:4041 doi: 10.1007/s10470-011-9609-6
Fig. 1.  Block diagram of the pipelined ADC architecture.

Fig. 2.  Two stages of 1.5 bit/stage sub-stage with working clock phase.

Fig. 4.  Block diagram of the DLL base clock generator.

Fig. 3.  Diagram of the CD pipelined ADC sub-stage and its operation waveform.

Fig. 7.  (a) Conventional and (b) the proposed bootstrapped switches.

Fig. 5.  Signal flow for the PFD.

Fig. 6.  Digital controlled delay cell.

Fig. 9.  Die photograph and measured results of the prototype ADC. (a) Die photograph. (b) SFDR and SNR versus input frequency. (c) FFT spectrum. (d) INL/DNL.

Fig. 8.  Circuit structure of SH circuit.

Table 1.   Performance summary.

[1]
Black W C, Hodges D A. Time interleaved converter arrays. IEEE J Solid-State Circuits, 1980, 15(6):1022 doi: 10.1109/JSSC.1980.1051512
[2]
Arias J, Boccuzzi V, Quintanilla L, et al. Low-power pipeline ADC for wireless LANs. IEEE J Solid-State Circuits, 2004, 39(8):1338 doi: 10.1109/JSSC.2004.831477
[3]
Min B M, Kim P, Bowman F W, et al. A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC. IEEE J Solid-State Circuits, 2003, 38(12):2031 doi: 10.1109/JSSC.2003.819166
[4]
Hsu C C, Huang F C, Shih C Y, et al. An 11 b 800 MS/s time-interleaved ADC with digital background calibration. IEEE ISSCC Dig Tech Papers, 2007:464 https://rd.springer.com/content/pdf/bbm%3A978-90-481-9716-3%2F1.pdf
[5]
Law C H, Hurst P J, Lewis S H. A four-channel time-interleaved ADC with digital calibration of inter-channel timing and memory errors. IEEE J Solid-State Circuits, 2010, 45(10):2091 doi: 10.1109/JSSC.2010.2061630
[6]
Buchanan J E. Bucket brigade analog-to-digital converter. US Patent, No. 4072938, 1978
[7]
Anthony M, Kohler E, Kurtze J, et al. A process-scalable low-power charge-domain 13-bit pipeline ADC. Symposium on VLSI Circuits, 2008:222 doi: 10.1007/978-90-481-3083-2_3/fulltext.html
[8]
Anthony M, Kurtze J. Charge domain pipelined analog to digital converter. US Patent, No. 7570192, 2009
[9]
Chen Z H, Yu Z G, Huang S R. et al. A PVT insensitive boosted charge transfer for high speed charge-domain pipelined ADCs. IEICE Electron Express, 2012, 9(6):565 doi: 10.1587/elex.9.565
[10]
Liang C K, Yang R J, Liu S I. An all-digital fast-locking programmable DLL-based clock generator. IEEE Trans Circuits Syst I:Regular Papers, 2008, 55(1):361 doi: 10.1109/TCSI.2007.913612
[11]
Abo A M, Gray P R. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J Solid-State Circuits, 1999, 34(5):599 doi: 10.1109/4.760369
[12]
Hu X Y, Zhou Y M. A CMOS sampling switch for 14 bit 50 MHz pipelined A/D converter. Chinese Journal of Semiconductors, 2007, 28(9):1808
[13]
Aksin D, Al-Shyoukh M, Maloberti F. Switch bootstrapping for precise sampling beyond supply voltage. IEEE J Solid-State Circuits, 2006, 41(8):1938 doi: 10.1109/JSSC.2006.875305
[14]
Xu Lai, Yin Xiumei, Yang Huazhong. A 10-bit 100 Msps low power time-interleaved ADC using OTA sharing. Journal of Semiconductors, 2010, 31(9):095012 doi: 10.1088/1674-4926/31/9/095012
[15]
Chu J, Lee H S. A 450 MS/s 10-bit time-interleaved zero-crossing based ADC. IEEE Custom Integrated Circuits Conference, 2011:1 doi: 10.1007/s10470-014-0299-8
[16]
Kim Y H, Lee J, Cho S H. A 10-bit 300 MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages. IEEE International Symposium on Circuits and Systems, 2010:4041 doi: 10.1007/s10470-011-9609-6
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    Received: 11 October 2012 Revised: 19 January 2013 Online: Published: 01 June 2013

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      Zhenhai Chen, Hongwen Qian, Songren Huang, Hong Zhang, Zongguang Yu. A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling[J]. Journal of Semiconductors, 2013, 34(6): 065005. doi: 10.1088/1674-4926/34/6/065005 Z H Chen, H W Qian, S R Huang, H Zhang, Z G Yu. A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling[J]. J. Semicond., 2013, 34(6): 065005. doi: 10.1088/1674-4926/34/6/065005.Export: BibTex EndNote
      Citation:
      Zhenhai Chen, Hongwen Qian, Songren Huang, Hong Zhang, Zongguang Yu. A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling[J]. Journal of Semiconductors, 2013, 34(6): 065005. doi: 10.1088/1674-4926/34/6/065005

      Z H Chen, H W Qian, S R Huang, H Zhang, Z G Yu. A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling[J]. J. Semicond., 2013, 34(6): 065005. doi: 10.1088/1674-4926/34/6/065005.
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      A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling

      doi: 10.1088/1674-4926/34/6/065005
      Funds:

      the 333 Talent Project of Jiangsu Province, China BRA2011115

      Project supported by the National Science Foundation of China (No. 61106027) and the 333 Talent Project of Jiangsu Province, China (No. BRA2011115)

      the National Science Foundation of China 61106027

      More Information
      • Corresponding author: Chen Zhenhai, Email:diaoyuds@126.com
      • Received Date: 2012-10-11
      • Revised Date: 2013-01-19
      • Published Date: 2013-06-01

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