SEMICONDUCTOR DEVICES

A novel NLDMOS with a high ballast resistance for ESD protection

Hang Fan and Bo Zhang

+ Author Affiliations

 Corresponding author: Fan Hang, fanmes@163.com

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Abstract: To prevent the non-uniform conduction phenomenon caused by the Kirk effect in an NLDMOS under ESD stress, a novel NLDMOS structure is proposed. High electron injection current is the base of Kirk effect. Higher electron injection can makes the Kirk effect more serious and lead easily to the non-uniform conduction phenomenon. By splitting the drain N+ with the field oxide in the proposed structure, the crowded current can lead to a higher voltage drop on the ballast resistance. Therefore, the non-uniform conduction is suppressed, and its failure current is much improved.

Key words: electro-static dischargeballast resistanceLDMOS



[1]
Shrivastava M, Gossner H. A review on the ESD robustness of drain-extended MOS devices. J Device Mater Reliab, 2012, 12(4):615 doi: 10.1109/TDMR.2012.2220358
[2]
[3]
Wang C T, Ker M D, Tang T H, et al. ESD protection design with lateral DMOS transistor in 40-V BCD technology. Symp Int Physical and Failure Analysis of Integrated Circuits, 2010 http://ieeexplore.ieee.org/document/5604306/?isnumber=5621692&arnumber=5604306
[4]
Walker A J, Puchner H, Dhanraj S P. High-voltage CMOS ESD and the safe operating area. Electron Devices, 2009, 56(8):1753 doi: 10.1109/TED.2009.2022698
[5]
Ker M D, Lai T H. Investigation on robustness of CMOS devices against cable discharge event (CDE) under different layout parameters in a deep-submicrometer CMOS technology. IEEE Trans Electromag Compatibility, 2008, 50(4):810 doi: 10.1109/TEMC.2008.2004582
[6]
Lee J C, Hoque A, Croft G D, et al. An electrostatic discharge failure mechanism in semiconductor devices, with applications to electrostatic discharge measurements using transmission line pulsing technique. Solid-State Electron, 2000, 44(10):1771 doi: 10.1016/S0038-1101(00)00122-2
[7]
Chen W Y, Ker M D, Jou Y N, et al. Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection. Symp Int Circuits and Systems, 2009 http://ieeexplore.ieee.org/document/5117766/
[8]
Cao Y, Glaser U. Statically triggered active ESD clamps for high-voltage applications. Symp Electrical Overstress/Electrostatic Discharge (EOS/ESD), 2012 http://ieeexplore.ieee.org/document/6333329/
[9]
Ker M D, Ker M D, Shieh W T, et al. New ballasting layout schemes to improve ESD robustness of I/O buffers in fully silicided CMOS process. Electron Devices, 2009, 56(12):3149 doi: 10.1109/TED.2009.2031003
Fig. 1.  Cross sections of the conventional NLDMOS.

Fig. 2.  TLP $I$-$V$ curve of the conventional NLDMOS.

Fig. 3.  1-D N+/Ndrift/Pw/N+ structure with 20 $\mu$m width.

Fig. 4.  Simulated voltage curves of the N+/Ndrift/Pw/N+ transistor under different current stresses.

Fig. 5.  Current density and electric field distribution along the width direction in the Ndrift region.

Fig. 6.  Current distribution in N+/Ndrift/Pw/N+ transistor at $t_4$ $=$ 58 ns.

Fig. 7.  Current filament formation process.

Fig. 8.  Cross sections of the proposed NLDMOS with HVNW ballast resistance.

Fig. 9.  Current distribution in (a) the conventional and (b) the proposed NLDMOS.

Fig. 10.  TLP $I$-$V$ curves of the LDMOS with N+ and HVNW ballast resistance.

[1]
Shrivastava M, Gossner H. A review on the ESD robustness of drain-extended MOS devices. J Device Mater Reliab, 2012, 12(4):615 doi: 10.1109/TDMR.2012.2220358
[2]
[3]
Wang C T, Ker M D, Tang T H, et al. ESD protection design with lateral DMOS transistor in 40-V BCD technology. Symp Int Physical and Failure Analysis of Integrated Circuits, 2010 http://ieeexplore.ieee.org/document/5604306/?isnumber=5621692&arnumber=5604306
[4]
Walker A J, Puchner H, Dhanraj S P. High-voltage CMOS ESD and the safe operating area. Electron Devices, 2009, 56(8):1753 doi: 10.1109/TED.2009.2022698
[5]
Ker M D, Lai T H. Investigation on robustness of CMOS devices against cable discharge event (CDE) under different layout parameters in a deep-submicrometer CMOS technology. IEEE Trans Electromag Compatibility, 2008, 50(4):810 doi: 10.1109/TEMC.2008.2004582
[6]
Lee J C, Hoque A, Croft G D, et al. An electrostatic discharge failure mechanism in semiconductor devices, with applications to electrostatic discharge measurements using transmission line pulsing technique. Solid-State Electron, 2000, 44(10):1771 doi: 10.1016/S0038-1101(00)00122-2
[7]
Chen W Y, Ker M D, Jou Y N, et al. Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection. Symp Int Circuits and Systems, 2009 http://ieeexplore.ieee.org/document/5117766/
[8]
Cao Y, Glaser U. Statically triggered active ESD clamps for high-voltage applications. Symp Electrical Overstress/Electrostatic Discharge (EOS/ESD), 2012 http://ieeexplore.ieee.org/document/6333329/
[9]
Ker M D, Ker M D, Shieh W T, et al. New ballasting layout schemes to improve ESD robustness of I/O buffers in fully silicided CMOS process. Electron Devices, 2009, 56(12):3149 doi: 10.1109/TED.2009.2031003
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    Received: 03 July 2013 Revised: 22 August 2013 Online: Published: 01 February 2014

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      Hang Fan, Bo Zhang. A novel NLDMOS with a high ballast resistance for ESD protection[J]. Journal of Semiconductors, 2014, 35(2): 024005. doi: 10.1088/1674-4926/35/2/024005 H Fan, B Zhang. A novel NLDMOS with a high ballast resistance for ESD protection[J]. J. Semicond., 2014, 35(2): 024005. doi: 10.1088/1674-4926/35/2/024005.Export: BibTex EndNote
      Citation:
      Hang Fan, Bo Zhang. A novel NLDMOS with a high ballast resistance for ESD protection[J]. Journal of Semiconductors, 2014, 35(2): 024005. doi: 10.1088/1674-4926/35/2/024005

      H Fan, B Zhang. A novel NLDMOS with a high ballast resistance for ESD protection[J]. J. Semicond., 2014, 35(2): 024005. doi: 10.1088/1674-4926/35/2/024005.
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      A novel NLDMOS with a high ballast resistance for ESD protection

      doi: 10.1088/1674-4926/35/2/024005
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      Project supported by the Important National S&T Special Project of China (No. 2010ZX02201-003-002)

      the Important National S&T Special Project of China 2010ZX02201-003-002

      More Information
      • Corresponding author: Fan Hang, fanmes@163.com
      • Received Date: 2013-07-03
      • Revised Date: 2013-08-22
      • Published Date: 2014-02-01

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