Fig. 1.
$H_{21}$ and $U$ of the DHBT with emitter area of 0.7 $\times$ 10 $\mu $ m$^{2}$ .
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| Citation: |
Youtao Zhang, Xiaopeng Li, Min Zhang, Wei Cheng, Xinyu Chen. A 83 GHz InP DHBT static frequency divider[J]. Journal of Semiconductors, 2014, 35(4): 045004. doi: 10.1088/1674-4926/35/4/045004
Y T Zhang, X P Li, M Zhang, W Cheng, X Y Chen. A 83 GHz InP DHBT static frequency divider[J]. J. Semicond., 2014, 35(4): 045004. doi: 10.1088/1674-4926/35/4/045004.
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Abstract
A static frequency divider is presented using 0.7 μm InP DHBTs with 280 GHz 1ft/fmax. The divider is based on ECL master-slave D-flip-flop topology with 30 HBTs and 20 resistors with a chip size 0.62×0.65 mm2. The circuits use peaking inductance as a part of the loads to maximize the highest clock rate. Momentum simulation is used to accurately characterize the effect of the clock feedback lines at the W band. Test results show that the divider can operate from 1 GHz up to 83 GHz. Its phase noise is 139 dBc/Hz with 100 kHz offset. The power dissipation of divider core is 350 mW.-
Keywords:
- high-speed,
- static frequency divider,
- InP DHBT
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References
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