A multimode DLL with trade-off between multiphase and static phase error

Dandan Zhang; Wenrui Zhu; Wei Li; Zhihong Huang; Lijiang Gao; Haigang Yang

doi:10.1088/1674-4926/35/5/055010

J. Semicond. > 2014, Volume 35 > Issue 5 > 055010, doi: 10.1088/1674-4926/35/5/055010

SEMICONDUCTOR INTEGRATED CIRCUITS

A multimode DLL with trade-off between multiphase and static phase error

Dandan Zhang^{1, 2}, Wenrui Zhu^{1, 2}, Wei Li¹, Zhihong Huang^{1, 2}, Lijiang Gao¹ and Haigang Yang^1,

+ Author Affiliations

Corresponding author: Yang Haigang, Email:yanghg@mail.ie.ac.cn

Abstract: A multimode DLL with trade-off between multiphase and static phase error is presented. By adopting a multimode control circuit to regroup the delay line, a better static phase error performance can be achieved while reducing the number of output phases. The DLL accomplishes three operation modes:mode1 with a four-phase output, mode2 with a two-phase output and a better static phase error performance, and mode3 with only a one-phase output but the best static phase error performance. The proposed DLL has been fabricated in 0.13 μm CMOS technology and measurement results show that the static phase errors of mode1, mode2 and mode3 are -18.2 ps, 11.8 ps and -6.44 ps, respectively, at 200 MHz. The measured RMS and peak-to-peak jitters of mode1, mode2 and mode3 are 2.0 ps, 2.2 ps, 2.1 ps and 10 ps, 9.3 ps, 10 ps respectively.

Key words: DLL, multimode, multiphase, static phase error

References

[1]	Chien G, Gray P R. A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS application. IEEE J Solid-State Circuits, 2000, 35(12):1995 http://www.academia.edu/1063532/A_900-MHz_local_oscillator_using_a_DLL-based_frequency_multiplier_technique_for_PCS_applications
[2]	Chang H H, Chang J Y, Kuo C Y, et al. A 0.7-2-GHz self-calibrated multiphase delay-locked loop. IEEE J Solid-State Circuits, 2006, 41(5):1051 doi: 10.1109/JSSC.2006.874036
[3]	Chang H H, Yang R J, Liu S I. Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection. IEEE Trans Circuit Syst I, Reg Papers, 2004, 51(12):2356 doi: 10.1109/TCSI.2004.838147
[4]	Kim Y S, Lee S K, Park H J, et al. A 110 MHz to 1.4 GHz locking 40-phase all-digital DLL. IEEE J Solid-State Circuits, 2011, 46(2):435 doi: 10.1109/JSSC.2010.2092996
[5]	Lin S C, Lee T C. An 833-MHz 132-phase multiphase clock generator with self-calibration circuits. IEEE Asian Solid-State Circuits Conference, 2008:437 http://iopscience.iop.org/export?articleId=1674-4926/35/5/055010&exportFormat=iopexport_bib&exportType=refs&navsubmit=Export%2Breferences
[6]	Bae J H, Seo J H, Yeo H S, et al. An all-digital 90-degree phase-shift dll with loop-embedded DCC for 1.6 Gbps DDR interface. IEEE Custom Integrated Circuits Conference (CICC), 2007:373 doi: 10.1007/s11432-014-5226-1
[7]	Chen Zhujia, Yang Haigang, Liu Fei, et al. A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA. Journal of Semiconductors, 2011, 32(10):105010 doi: 10.1088/1674-4926/32/10/105010
[8]	Zhang D, Yang H, Chen Z, et al. A fast-locking digital DLL with a high resolution time-to-digital converter. IEEE Custom Integrated Circuits Conference (CICC), 2013:1 http://www.ijsr.net/archive/v4i7/SUB156578.pdf
[9]	Lin W M, Teng K F, Liu S I. A delay-locked loop with digital background calibration. IEEE Asian Solid-State Circuits Conference, 2009:317 http://www.eecg.utoronto.ca/~tcc/samarah_cicc2012.pdf
[10]	Ryu K, Jung D H, Jung S O. A DLL with dual edge triggered phase detector for fast lock and low jitter clock generator. IEEE Trans Circuits Syst I:Regular Papers (TSCAS-I), 2012, 59(9):1860 doi: 10.1109/TCSI.2011.2180453
[11]	Park J H, Jung D H, Ryu K, et al. ADDLL for clock-Deskew buffer in high-performance SoCs. IEEE Trans Very Large Scale Integration (VLSI) Syst, 2013, 21(7):1368 doi: 10.1109/TVLSI.2012.2210742
[12]	Jung D H, Ryu K, Park J H, et al. A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. Proceedings of the ESSCIRC (ESSCIRC), 2012:181 doi: 10.1007/s11432-014-5226-1

Fig. 1. (a) A conventional DL. (b) Timing diagram of the conventional DL.

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Fig. 2. The architecture and timing diagram of a DL in three modes. (a) Mode1 with four-phase output clock. (b) Mode2 with two-phase output clock. (c) Mode3 with one-phase output clock.

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Fig. 3. Concept of the first control code calibration of four cases in mode2. (a) Tuning one step. (b) Holding. (c) Holding. (d) Tuning two steps.

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Fig. 4. Concept of the first control code calibration of eight cases in mode3. (a) Tuning two steps. (b) Tuning one step. (c) Tuning one step. (d) Holding. (e) Holding. (f) Tuning four steps. (g) Tuning four steps. (h) Tuning three steps.

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Fig. 5. (a) Architecture diagram of the proposed DLL. (b), (c), (d) Timing diagram of the proposed DLL working at Mode1, Mode2 and Mode3 respectively.

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Fig. 6. The block diagram of DCDL

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Fig. 7. (a) Block diagram of MCC. (b) Simplified diagram in mode2. (c) Simplified diagram in mode3.

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Fig. 8. Chip micrograph of the proposed DLL.

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Fig. 9. (a) Measured phase error and (b) histogram of mode1 at 200 MHz.

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Fig. 10. (a) Measured phase errors and (b) Histogram of mode2 at 200 MHz.

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Fig. 11. (a) Measured phase errors and (b) Histogram of mode3 at 200 MHz.

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Fig. 12. Measured output jitters of three modes at 200 MHz. (a) Mode1. (b) Mode2. (c) Mode3.

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Fig. 13. Measured phase errors of three modes versus input frequencies.

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Fig. 14. Measured p-p and RMS jitters versus input frequencies.

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Table 1. Performance comparison

[1]	Chien G, Gray P R. A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS application. IEEE J Solid-State Circuits, 2000, 35(12):1995 http://www.academia.edu/1063532/A_900-MHz_local_oscillator_using_a_DLL-based_frequency_multiplier_technique_for_PCS_applications
[2]	Chang H H, Chang J Y, Kuo C Y, et al. A 0.7-2-GHz self-calibrated multiphase delay-locked loop. IEEE J Solid-State Circuits, 2006, 41(5):1051 doi: 10.1109/JSSC.2006.874036
[3]	Chang H H, Yang R J, Liu S I. Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection. IEEE Trans Circuit Syst I, Reg Papers, 2004, 51(12):2356 doi: 10.1109/TCSI.2004.838147
[4]	Kim Y S, Lee S K, Park H J, et al. A 110 MHz to 1.4 GHz locking 40-phase all-digital DLL. IEEE J Solid-State Circuits, 2011, 46(2):435 doi: 10.1109/JSSC.2010.2092996
[5]	Lin S C, Lee T C. An 833-MHz 132-phase multiphase clock generator with self-calibration circuits. IEEE Asian Solid-State Circuits Conference, 2008:437 http://iopscience.iop.org/export?articleId=1674-4926/35/5/055010&exportFormat=iopexport_bib&exportType=refs&navsubmit=Export%2Breferences
[6]	Bae J H, Seo J H, Yeo H S, et al. An all-digital 90-degree phase-shift dll with loop-embedded DCC for 1.6 Gbps DDR interface. IEEE Custom Integrated Circuits Conference (CICC), 2007:373 doi: 10.1007/s11432-014-5226-1
[7]	Chen Zhujia, Yang Haigang, Liu Fei, et al. A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA. Journal of Semiconductors, 2011, 32(10):105010 doi: 10.1088/1674-4926/32/10/105010
[8]	Zhang D, Yang H, Chen Z, et al. A fast-locking digital DLL with a high resolution time-to-digital converter. IEEE Custom Integrated Circuits Conference (CICC), 2013:1 http://www.ijsr.net/archive/v4i7/SUB156578.pdf
[9]	Lin W M, Teng K F, Liu S I. A delay-locked loop with digital background calibration. IEEE Asian Solid-State Circuits Conference, 2009:317 http://www.eecg.utoronto.ca/~tcc/samarah_cicc2012.pdf
[10]	Ryu K, Jung D H, Jung S O. A DLL with dual edge triggered phase detector for fast lock and low jitter clock generator. IEEE Trans Circuits Syst I:Regular Papers (TSCAS-I), 2012, 59(9):1860 doi: 10.1109/TCSI.2011.2180453
[11]	Park J H, Jung D H, Ryu K, et al. ADDLL for clock-Deskew buffer in high-performance SoCs. IEEE Trans Very Large Scale Integration (VLSI) Syst, 2013, 21(7):1368 doi: 10.1109/TVLSI.2012.2210742
[12]	Jung D H, Ryu K, Park J H, et al. A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. Proceedings of the ESSCIRC (ESSCIRC), 2012:181 doi: 10.1007/s11432-014-5226-1

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Received: 23 November 2013 Revised: 12 December 2013 Online: Published: 01 May 2014

Article Navigation > Journal of Semiconductors > 2014 > 35(5): 055010

Dandan Zhang, Wenrui Zhu, Wei Li, Zhihong Huang, Lijiang Gao, Haigang Yang. A multimode DLL with trade-off between multiphase and static phase error[J]. Journal of Semiconductors, 2014, 35(5): 055010. doi: 10.1088/1674-4926/35/5/055010 Dandan Zhang and A Zhang, W R Zhu, W Li, Z H Huang, L J Gao, H G Yang. A multimode DLL with trade-off between multiphase and static phase error[J]. J. Semicond., 2014, 35(5): 055010. doi: 10.1088/1674-4926/35/5/055010.Export: BibTex EndNote

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Dandan Zhang, Wenrui Zhu, Wei Li, Zhihong Huang, Lijiang Gao, Haigang Yang. A multimode DLL with trade-off between multiphase and static phase error[J]. Journal of Semiconductors, 2014, 35(5): 055010. doi: 10.1088/1674-4926/35/5/055010

Dandan Zhang and A Zhang, W R Zhu, W Li, Z H Huang, L J Gao, H G Yang. A multimode DLL with trade-off between multiphase and static phase error[J]. J. Semicond., 2014, 35(5): 055010. doi: 10.1088/1674-4926/35/5/055010.

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A multimode DLL with trade-off between multiphase and static phase error

doi: 10.1088/1674-4926/35/5/055010

1.
Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China
2.
University of Chinese Academy of Sciences, Beijing 100049, China

Funds:

the National Natural Science Foundation of China 61106025

the National Science and Technology Major Project of China 2013ZX03006004

the CAS/SAFEA International Partnership Program for Creative Research Teams

Project supported by the National Science and Technology Major Project of China (No. 2013ZX03006004), the National Natural Science Foundation of China (No. 61106025), and the CAS/SAFEA International Partnership Program for Creative Research Teams

More Information

Corresponding author: Yang Haigang, Email:yanghg@mail.ie.ac.cn
Received Date: 2013-11-23
Revised Date: 2013-12-12
Published Date: 2014-05-01

Abstract

Abstract

A multimode DLL with trade-off between multiphase and static phase error is presented. By adopting a multimode control circuit to regroup the delay line, a better static phase error performance can be achieved while reducing the number of output phases. The DLL accomplishes three operation modes:mode1 with a four-phase output, mode2 with a two-phase output and a better static phase error performance, and mode3 with only a one-phase output but the best static phase error performance. The proposed DLL has been fabricated in 0.13 μm CMOS technology and measurement results show that the static phase errors of mode1, mode2 and mode3 are -18.2 ps, 11.8 ps and -6.44 ps, respectively, at 200 MHz. The measured RMS and peak-to-peak jitters of mode1, mode2 and mode3 are 2.0 ps, 2.2 ps, 2.1 ps and 10 ps, 9.3 ps, 10 ps respectively.
- DLL,
- multimode,
- multiphase,
- static phase error

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References(12)

References

[1]	Chien G, Gray P R. A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS application. IEEE J Solid-State Circuits, 2000, 35(12):1995 http://www.academia.edu/1063532/A_900-MHz_local_oscillator_using_a_DLL-based_frequency_multiplier_technique_for_PCS_applications
[2]	Chang H H, Chang J Y, Kuo C Y, et al. A 0.7-2-GHz self-calibrated multiphase delay-locked loop. IEEE J Solid-State Circuits, 2006, 41(5):1051 doi: 10.1109/JSSC.2006.874036
[3]	Chang H H, Yang R J, Liu S I. Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection. IEEE Trans Circuit Syst I, Reg Papers, 2004, 51(12):2356 doi: 10.1109/TCSI.2004.838147
[4]	Kim Y S, Lee S K, Park H J, et al. A 110 MHz to 1.4 GHz locking 40-phase all-digital DLL. IEEE J Solid-State Circuits, 2011, 46(2):435 doi: 10.1109/JSSC.2010.2092996
[5]	Lin S C, Lee T C. An 833-MHz 132-phase multiphase clock generator with self-calibration circuits. IEEE Asian Solid-State Circuits Conference, 2008:437 http://iopscience.iop.org/export?articleId=1674-4926/35/5/055010&exportFormat=iopexport_bib&exportType=refs&navsubmit=Export%2Breferences
[6]	Bae J H, Seo J H, Yeo H S, et al. An all-digital 90-degree phase-shift dll with loop-embedded DCC for 1.6 Gbps DDR interface. IEEE Custom Integrated Circuits Conference (CICC), 2007:373 doi: 10.1007/s11432-014-5226-1
[7]	Chen Zhujia, Yang Haigang, Liu Fei, et al. A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA. Journal of Semiconductors, 2011, 32(10):105010 doi: 10.1088/1674-4926/32/10/105010
[8]	Zhang D, Yang H, Chen Z, et al. A fast-locking digital DLL with a high resolution time-to-digital converter. IEEE Custom Integrated Circuits Conference (CICC), 2013:1 http://www.ijsr.net/archive/v4i7/SUB156578.pdf
[9]	Lin W M, Teng K F, Liu S I. A delay-locked loop with digital background calibration. IEEE Asian Solid-State Circuits Conference, 2009:317 http://www.eecg.utoronto.ca/~tcc/samarah_cicc2012.pdf
[10]	Ryu K, Jung D H, Jung S O. A DLL with dual edge triggered phase detector for fast lock and low jitter clock generator. IEEE Trans Circuits Syst I:Regular Papers (TSCAS-I), 2012, 59(9):1860 doi: 10.1109/TCSI.2011.2180453
[11]	Park J H, Jung D H, Ryu K, et al. ADDLL for clock-Deskew buffer in high-performance SoCs. IEEE Trans Very Large Scale Integration (VLSI) Syst, 2013, 21(7):1368 doi: 10.1109/TVLSI.2012.2210742
[12]	Jung D H, Ryu K, Park J H, et al. A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. Proceedings of the ESSCIRC (ESSCIRC), 2012:181 doi: 10.1007/s11432-014-5226-1

A multimode DLL with trade-off between multiphase and static phase error

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