Fig. 1.
(a) Schematic diagram of the CNFET device. (b) SB-CNFET. (c) T-CNFET. (d) MOSFET-like CNFET.
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P. A. Gowri Sankar, K. Udhayakumar. MOSFET-like CNFET based logic gate library for low-power application: a comparative study[J]. Journal of Semiconductors, 2014, 35(7): 075001. doi: 10.1088/1674-4926/35/7/075001
P. A. G. Sankar, K. Udhayakumar. MOSFET-like CNFET based logic gate library for low-power application: a comparative study[J]. J. Semicond., 2014, 35(7): 075001. doi: 10.1088/1674-4926/35/7/075001.
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MOSFET-like CNFET based logic gate library for low-power application: a comparative study
doi: 10.1088/1674-4926/35/7/075001
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Abstract
The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely:complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries. -
References
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