SEMICONDUCTOR DEVICES

Insights into channel potentials and electron quasi-Fermi potentials for DGtunnel FETs

Menka, Anand Bulusu and S. Dasgupta

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 Corresponding author: Anand Bulusu, Email: sudebfec@iitr.ernet.in

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Abstract: A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potentials on the device characteristics of a silicon double-gate tunnel field effect transistor (Si-DG TFET) is reported in this paper. The investigation is mainly aimed at studying electrical properties such as the electric potential, the electron density, and the electron quasi-Fermi potential in a channel. From the simulation results, it is found that the electrical properties in the channel region of the DG TFET are different from those for a DG MOSFET. It is observed that the central channel potential of the DG TFET is not pinned to a fixed potential even after the threshold is passed (as in the case of the DG MOSFET); instead, it initially increases and later on decreases with increasing gate voltage, and this is also the behavior exhibited by the surface potential of the device. However, the drain current always increases with the applied gate voltage. It is also observed that the electron quasi-Fermi potential (eQFP) decreases as the channel potential starts to decrease, and there are hiphops in the channel eQFP for higher applied drain voltages. The channel regime resistance is also observed for higher gate length, which has a great effect on the I-V characteristics of the DG TFET device. These channel regime electrical properties will be very useful for determining the tunneling current; thus these results may have further uses in developing analytical current models.

Key words: Si-DG TFETelectron quasi-Fermi potentialI-V characteristicsdrain extension regime resistanceresistive dropchannel properties



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Fig. 1.  Double-gate tunnel FET device structure. (a) The double-gate tunnel FET device structure under study. (b) The double-gate tunnel FET device resistive equivalent, where $R_{\rm S}$, $R_{\rm C}$ and $R_{\rm D}$ are the extension regime resistances of the source, channel and drain respectively, while $R_{\rm T}$ is the tunneling junction resistance which is a strong function of the applied gate voltage, $V_{\rm gs}$.

Fig. 2.  $I_{\rm ds}$-$V_{\rm gs}$ calibration with the work previously reported in Reference [8]; for this calibration all physical dimensions are taken from Reference [8], and then the tuning for carrier effective masses and lifetimes is done in order to calibrate the results.

Fig. 3.  (Color online) Energy band diagrams for the conduction band, valence band, and electron and hole quasi-Fermi levels, Here, corresponding to a set of $V_{\rm gs}$ and $V_{\rm ds}$, there is a single color-see the legends given in the figures. The uppermost and lowermost same colored graphs show conduction band and valence band energies respectively; the dashed line type is for electron quasi-Fermi energy levels and the dot-dashed line type is for hole quasi-Fermi energy levels.

Fig. 4.  Variations with applied gate drain voltage of the (a) midchannel potential, (b) surface potential and (c) electron quasi-Fermi potential with varying drain voltage $V_{\rm ds}$ (from 0 to 1.0 V).

Fig. 5.  DG TFET structure with zero source and drain extension regime resistances: (a) the device structure under simulation and (b) the resistive equivalent circuit for (a); here both $R_{\rm T}$ and $R_{\rm C}$ depend on $V_{\rm gs}$ and $V_{\rm ds}$.

Fig. 6.  Variations with applied gate drain voltage in (a) the midchannel potential, (b) the surface potential and (c) the electron quasi-Fermi potentials with varying drain voltage $V_{\rm ds}$ (from 0 to 1.0 V) for the TFET structure given in Figure 5.

Fig. 7.  Variations in midchannel electron density with applied gate, $V_{\rm gs}$, and drain, $V_{\rm ds}$, voltages on a log scale are plotted here. The inset represents the electron density on a linear scale for higher gate voltages.

Fig. 8.  Variations in surface electron density with applied gate, $V_{\rm gs}$, and drain, $V_{\rm ds}$, voltages on a log scale are plotted here. The inset represents the electron density on a linear scale for higher gate voltages.

Fig. 9.  Variations with applied gate drain voltage in (a) the midchannel potential, (b) the surface potential and (c) the electron quasi-Fermi potentials with varying channel length, from 50 to 500 nm, at drain voltage $V_{\rm ds}=1.0$ V, for the TFET structure given in Figure 5.

Fig. 10.  Drain current, $I_{\rm ds}$, versus applied gate voltage, $V_{\rm gs}$, plots for various drain voltages, $V_{\rm ds}$; the dotted lines denote the case without an $I_{\rm ds}R_{\rm D}$ drop, while the solid lines denote the $I$-$V$ characteristics with an $I_{\rm ds}R_{\rm D}$ drop.

Table 1.   Double-gate tunnel FET device parameters.

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    Received: 04 June 2014 Revised: Online: Published: 01 January 2015

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      Menka, Anand Bulusu, S. Dasgupta. Insights into channel potentials and electron quasi-Fermi potentials for DGtunnel FETs[J]. Journal of Semiconductors, 2015, 36(1): 014005. doi: 10.1088/1674-4926/36/1/014005 Menka, A. Bulusu, S. Dasgupta. Insights into channel potentials and electron quasi-Fermi potentials for DGtunnel FETs[J]. J. Semicond., 2015, 36(1): 014005. doi:  10.1088/1674-4926/36/1/014005.Export: BibTex EndNote
      Citation:
      Menka, Anand Bulusu, S. Dasgupta. Insights into channel potentials and electron quasi-Fermi potentials for DGtunnel FETs[J]. Journal of Semiconductors, 2015, 36(1): 014005. doi: 10.1088/1674-4926/36/1/014005

      Menka, A. Bulusu, S. Dasgupta. Insights into channel potentials and electron quasi-Fermi potentials for DGtunnel FETs[J]. J. Semicond., 2015, 36(1): 014005. doi:  10.1088/1674-4926/36/1/014005.
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      Insights into channel potentials and electron quasi-Fermi potentials for DGtunnel FETs

      doi: 10.1088/1674-4926/36/1/014005
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      • Corresponding author: Email: sudebfec@iitr.ernet.in
      • Received Date: 2014-06-04
      • Accepted Date: 2014-09-03
      • Published Date: 2015-01-25

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