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A 0.8-4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications

Yuanxin Zhao, Yuanpei Gao, Wei Li, Ning Li and Junyan Ren

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 Corresponding author: Wei Li, E-mail: w-li@fudan.edu.cn

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Abstract: A 0.8-4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper. Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the "pulse-swallowing" phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary. The measurement results show that the output frequency range of this frequency synthesizer is 0.8-4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached-100 dBc/Hz, and-125 dBc/Hz respectively. The lowest reference spur is-58 dBc.

Key words: fractional-N frequency synthesizerall-digital phase-locked loopphase noisereference spurCMOS



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Fig. 1.  The conventional fractional-$N$ ADPLL block diagram with feedback divider.

Fig. 2.  The proposed ADPLL based frequency synthesizer for wireless communications.

Fig. 3.  The modeling of this ADPLL architecture.

Fig. 4.  GRO TDC structure.

Fig. 5.  The 11-stages GRO structure.

Fig. 6.  Quantization error of GRO.

Fig. 7.  Structure of the phase-frequency detector.

Fig. 8.  Structure of the arbiter.

Fig. 9.  Multi-phase counter structure.

Fig. 10.  Structure of the asynchronous reset TSPCR.

Fig. 11.  "Pulse-swallowing" phenomenon in GRO-based TDC.

Fig. 12.  Structure of the proposed overflow counter.

Fig. 13.  Structure of the DLF.

Fig. 14.  Operation of NTW-clamp circuit.

Fig. 15.  The conventional structure of the division-ratio-variable integer divider.

Fig. 16.  The improved structure of the division-ratio-variable integer divider proposed in this design.

Fig. 17.  The circuit of delay-variable inverter chain.

Fig. 18.  The proposed dual-band DCO.

Fig. 19.  A simplified fine tuning bank using the proposed varactor.

Fig. 20.  The $C$-$V$ characteristic of the proposed varactor.

Fig. 21.  The structure of the DCO in this ADPLL based frequency synthesizer.

Fig. 22.  Microphotograph of the ADPLL based frequency synthesizer.

Fig. 23.  Test PCB of the ADPLL chip in a COB package.

Fig. 24.  Measurement of TDC when $f_{\rm CKV}$ is 41.67 MHz.

Fig. 25.  Measurement of TDC when $f_{\rm CKV}$ is 38.46 MHz.

Fig. 26.  Frequency tuning curve of high-band DCO.

Fig. 27.  Frequency tuning curve of low-band DCO.

Fig. 28.  Open-loop phase noise of the DCO at 3.2 GHz.

Fig. 29.  Open-loop frequency spectrum of the DCO at 3.2 GHz.

Fig. 30.  Transient locking curves with the overflow counter bypassed at 2.68 GHz.

Fig. 31.  Transient locking curves with the overflow counter enabled at 2.68 GHz.

Fig. 32.  Measurement result of phase noise at 900 MHz.

Fig. 33.  Frequency spectrum at 900 MHz.

Fig. 34.  Measurement result of phase noise at 4.24 GHz.

Fig. 35.  Frequency spectrum at 4.24 GHz.

Fig. 36.  In-band and out-band PN at 10 kHz and 1 MHz offset from 0.8-4.2 GHz.

Fig. 37.  The modeling result of the output phase noise at 2.08 GHz.

Fig. 38.  The measurement result of the output phase noise at 2.08 GHz.

Fig. 39.  Reference spur at 40 MHz offset from 0.8-4.2 GHz.

Fig. 40.  Simulation results of the reference spur at (a) 2.4975 GHz, (b) 3.03 GHz, and (c) 3.71 GHz.

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Table 1.   Output ways of different communication standards.

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Table 2.   Performance summary and comparison.

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    Received: 23 June 2014 Revised: Online: Published: 01 January 2015

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      Yuanxin Zhao, Yuanpei Gao, Wei Li, Ning Li, Junyan Ren. A 0.8-4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications[J]. Journal of Semiconductors, 2015, 36(1): 015001. doi: 10.1088/1674-4926/36/1/015001 Y X Zhao, Y P Gao, W Li, N Li, J Y Ren. A 0.8-4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications[J]. J. Semicond., 2015, 36(1): 015001. doi: 10.1088/1674-4926/36/1/015001.Export: BibTex EndNote
      Citation:
      Yuanxin Zhao, Yuanpei Gao, Wei Li, Ning Li, Junyan Ren. A 0.8-4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications[J]. Journal of Semiconductors, 2015, 36(1): 015001. doi: 10.1088/1674-4926/36/1/015001

      Y X Zhao, Y P Gao, W Li, N Li, J Y Ren. A 0.8-4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications[J]. J. Semicond., 2015, 36(1): 015001. doi: 10.1088/1674-4926/36/1/015001.
      Export: BibTex EndNote

      A 0.8-4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications

      doi: 10.1088/1674-4926/36/1/015001
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      Project supported by the National Natural Science Foundation of China (No. 61176029) and the National Twelve-Five Project (No. 513***).

      More Information
      • Corresponding author: E-mail: w-li@fudan.edu.cn
      • Received Date: 2014-06-23
      • Accepted Date: 2014-07-22
      • Published Date: 2015-01-25

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