A 16 b 2 GHz digital-to-analog converter in 0.18 <i>μ</i>m CMOS with digital calibration technology

Weidong Yang; Jiandong Zang; Tiehu Li; Pu Luo; Jie Pu; Ruitao Zhang; Chao Chen

doi:10.1088/1674-4926/36/10/105002

J. Semicond. > 2015, Volume 36 > Issue 10 > 105002, doi: 10.1088/1674-4926/36/10/105002

SEMICONDUCTOR INTEGRATED CIRCUITS

A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

Weidong Yang¹, Jiandong Zang², Tiehu Li², Pu Luo², Jie Pu¹, Ruitao Zhang¹ and Chao Chen¹

+ Author Affiliations

Abstract: This paper presents a 16-bit 2 GSPS digital-to-analog converter (DAC) in 0.18μm CMOS technology.This DAC is implemented using time division multiplex access system architecture in the digital domain.The input data is received with a two-channel LVDS interface.The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock.A FIFO is designed to absorb the phase difference between the data clock and DAC system clock.A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS.The current source mismatch at higher bits is calibrated in the digital domain.Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB INL less than ±4.3 LSB after the chip is calibrated.

Key words: digital-to-analog converter (DAC), time-interleaving configuration, delay lock loop (DLL), digital calibration

References

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Fig. 1. Functional block diagram.

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Fig. 2. Block diagram of analog delay lock loop DLL.

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Fig. 3. Configuration of FIFO.

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Fig. 4. Decoding and randomization unit.

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Fig. 5. Functional block diagram of timing adjustment unit.

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Fig. 6. Calibration principle of higher 5 bits.

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Fig. 7. The Min(Max$\vert $INL$\vert )$ criterion with DNL constraint.

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Fig. 8. Simulation results of DNL before and after calibration.

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Fig. 9. Simulation results of INL before and after calibration.

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Fig. 10. Die photo of the DAC.

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Fig. 11. Evaluation board for the DAC.

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Fig. 12. Test results of DNL (a) before and (b) after calibration.

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Fig. 13. Test results of INL (a) before and (b) after calibration.

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Fig. 14. Test curve of SFDR @ $f_{\rm CLK}$ $=$ 2 GHz,$f_{\rm OUT}$ $=$ 36 MHz.

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Fig. 15. Test curve of SFDR @ $f_{\rm CLK}$ $=$ 2 GHz,$f_{\rm OUT}$ $=$ 830 MHz.

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Table 1. Measured electrical characteristics of the DAC.

Parameter	Measured results
Power supply	1.8 V/3.3 V
Resolution	16 bit
Maximum update rate	2.2 GSPS
DNL	±5.2 LSB (intrinsic)
DNL	±2.1 LSB (calibrated)
INL	±12.7 LSB (intrinsic)
INL	±4.3 LSB (calibrated)
NSD	-155 dBm/Hz @ f_DAC=2 GHz,f_OUT=36 MHz
SFDR	74.02 dBc @ f_DAC=2 GHz,f_OUT=36 MHz,intrinsic
	77.61 dBc @ f_DAC=2 GHz,f_OUT=36 MHz,calibrated
	46.73 dBc @ f_DAC=2 GHz,f_OUT=830 MHz,intrinsic
	48.06 dBc @ f_DAC=2 GHz,f_OUT=830 MHz,calibrated
Power	930 mW @ f_DAC=2 GHz

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Table 2. Performance compared with similar product.

Parameter	This work	DAC5681	AD9739	DAC5670	AD9142
Channel	Single	Single	Single	Single	Dual
Technology	180 nm CMOS	180 nm CMOS	180 nm CMOS	180 nm BiCMOS	180 nm CMOS
Update	2.2 GSPS	1 GSPS	2.5 GSPS	2.4 GSPS	1.6 GSPS
Resolution (bit)	16	16	14	14	1.6
DNL (LSB)	±2.1	±2	±0.8	±1.75	±2.1
INL (LSB)	±4.3	±4	±1.3	±7.5	±3.7
SFDR (dBc)	77.6 @ f_DAC=2 GHz,f_OUT=36 MHz,0 dFS	77 @ f_DAC=1 GHz,f_OUT=20.1 MHz,0 dFS	69.5 @ f_DAC=2.4 GHz,f_OUT=100 MHz,0 dFS	46 @ f_DAC=2.4 GHz,f_OUT=100 MHz,0 dFS	80 @ f_DAC=1.474 GHz,f_OUT=280 MHz,-14 dFS
Power (mW)	930	830	1160	2350	1815

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Received: 19 March 2015 Revised: Online: Published: 01 October 2015

This paper presents a 16-bit 2 GSPS digital-to-analog converter (DAC) in 0.18μm CMOS technology.This DAC is implemented using time division multiplex access system architecture in the digital domain.The input data is received with a two-channel LVDS interface.The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock.A FIFO is designed to absorb the phase difference between the data clock and DAC system clock.A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS.The current source mismatch at higher bits is calibrated in the digital domain.Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB INL less than ±4.3 LSB after the chip is calibrated.

A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

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