SEMICONDUCTOR INTEGRATED CIRCUITS

A single-ended 10-bit 200 kS/s 607 μW SAR ADC with an auto-zeroing offset cancellation technique

Weiru Gu1, Yimin Wu1, Fan Ye1 and Junyan Ren1, 2,

+ Author Affiliations

 Corresponding author: Ren Junyan, jyren@fudan.edu.cn

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Abstract: This paper presents a single-ended 8-channel 10-bit 200 kS/s 607 μW synchronous successive approximation register (SAR) analog-to-digital converter (ADC) using HLMC 55 nm low leakage (LL) CMOS technology with a 3.3 V/1.2 V supply voltage.In conventional binary-encoded SAR ADCs the total capacitance grows exponentially with resolution.In this paper a CR hybrid DAC is adopted to reduce both capacitance and core area.The capacitor array resolves 4 bits and the other 6 bits are resolved by the resistor array.The 10-bit data is acquired by thermometer encoding to reduce the probability of DNL errors which are typically present in binary weighted architectures.This paper uses an auto-zeroing offset cancellation technique that can reduce the offset to 0.286 mV.The prototype chip realized the 10-bit SAR ADC fabricated in HLMC 55 nm CMOS technology with a core area of 167×87 μm2.It shows a sampling rate of 200 kS/s and low power dissipation of 607 μW operates at a 3.3 V analog supply voltage and a 1.2 V digital supply voltage.At the input frequency of 10 kHz the signal-to-noise-anddistortion ratio (SNDR) is 60.1 dB and the spurious-free dynamic range (SFDR) is 68.1 dB.The measured DNL is +0.37/-0.06 LSB and INL is +0.58/-0.22 LSB.

Key words: analog-to-digital converterCR hybrid DACthermometer encodingauto-zero offset cancellationsuccessive approximation register



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Fig. 1.  Block diagram of the ADC.

Fig. 2.  CR hybrid DAC structure.

Fig. 3.  Layout structure of fringing capacitor.

Fig. 4.  Binary to thermometer encoding based on matrix selection simplification.

Fig. 5.  Auto-zeroed comparator and timing diagram.

Fig. 6.  (a) Pre-amplifier. (b) Self-biasing circuit.

Fig. 7.  Latch.

Fig. 8.  Monte Carlo simulation results.

Fig. 9.  (a) 3.3 to1.2 V level shifter. (b) 1.2 to 3.3 V level shifter.

Fig. 10.  Clock generator and timing diagram.

Fig. 11.  Die photograph of a prototype of ADC.

Fig. 12.  Measured static performance. (a) DNL. (b) INL.

Fig. 13.  Measured FFT plots ($F_{\rm s}$ $=$ 200 kS/s). (a) $F_{\rm in}$ $=$ 10 kHz. (b) $F_{\rm in}$ $=$ 99 kHz.

Fig. 14.  Measured dynamic performance versus input frequency ($F_{\rm s}$ $=$ 200 kS/s

Table 1.   Performance comparison with other IP core.

ParameterThis workReference [9]Reference [10]
Resolution (bit)101210
Sampling rate (kS/s)2001251000
INL/DNL (LSB)0.58/0.372/2N/A
Power ($\mu$W)607>8644290
Supply (V)3.3/1.22.7-5.25(2.5-3.6)/1.2
FoM (pJ/conv-step)3.6>1.7>4.2
Process55 nm CMOSN/A90 nm CMOS
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    Received: 19 January 2015 Revised: Online: Published: 01 October 2015

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      Weiru Gu, Yimin Wu, Fan Ye, Junyan Ren. A single-ended 10-bit 200 kS/s 607 μW SAR ADC with an auto-zeroing offset cancellation technique[J]. Journal of Semiconductors, 2015, 36(10): 105006. doi: 10.1088/1674-4926/36/10/105006 W R Gu, Y M Wu, F Ye, J Y Ren. A single-ended 10-bit 200 kS/s 607 μW SAR ADC with an auto-zeroing offset cancellation technique[J]. J. Semicond., 2015, 36(10): 105006. doi: 10.1088/1674-4926/36/10/105006.Export: BibTex EndNote
      Citation:
      Weiru Gu, Yimin Wu, Fan Ye, Junyan Ren. A single-ended 10-bit 200 kS/s 607 μW SAR ADC with an auto-zeroing offset cancellation technique[J]. Journal of Semiconductors, 2015, 36(10): 105006. doi: 10.1088/1674-4926/36/10/105006

      W R Gu, Y M Wu, F Ye, J Y Ren. A single-ended 10-bit 200 kS/s 607 μW SAR ADC with an auto-zeroing offset cancellation technique[J]. J. Semicond., 2015, 36(10): 105006. doi: 10.1088/1674-4926/36/10/105006.
      Export: BibTex EndNote

      A single-ended 10-bit 200 kS/s 607 μW SAR ADC with an auto-zeroing offset cancellation technique

      doi: 10.1088/1674-4926/36/10/105006
      Funds:

      Project supported by the National Science and Technology Support Program of China (No.2012BAI13B07) and the National Science and Technology Major Project of China (No.2012ZX03001020-003).

      More Information
      • Corresponding author: Ren Junyan, jyren@fudan.edu.cn
      • Received Date: 2015-01-19
      • Accepted Date: 2015-04-12
      • Published Date: 2015-01-25

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