J. Semicond. > 2015, Volume 36 > Issue 11 > 111001, doi: 10.1088/1674-4926/36/11/111001

INVITED REVIEW PAPERS

Single event soft error in advanced integrated circuit

Yuanfu Zhao1, Suge Yue1, 2, Xinyuan Zhao1, , Shijin Lu1, Qiang Bian1, Liang Wang1 and Yongshu Sun1

+ Author Affiliations

 Corresponding author: Zhao Xinyuan, Email: denniso@163.com

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Abstract: As technology feature sizes decrease, single event upset (SEU), and single event transient (SET) dominate the radiation response of microcircuits. Multiple bit upset (MBU) (or multi cell upset) effects, digital single event transient (DSET) and analogue single event transient (ASET) caused serious problems for advanced integrated circuits (ICs) applied in a radiation environment and have become a pressing issue. To face this challenge, a lot of work has been put into the single event soft error mechanism and mitigation schemes. This paper presents a review of SEU and SET, including: a brief historical overview, which summarizes the historical development of the SEU and SET study since their first observation in the 1970's; effects prominent in advanced technology, which reviews the effects such as MBU, MSET as well as SET broadening and quenching with the influence of temperature, device structure etc.; the present understanding of single event soft error mechanisms, which review the basic mechanism of single event generation including various component of charge collection; and a discussion of various SEU and SET mitigation schemes divided as circuit hardening and layout hardening that could help the designer meet his goals.

Key words: SET, SEU, MCU, advanced technology



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Fig. 1.  Percentage of SBU and MCU (130-65 nm).

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Fig. 2.  (Color online) Soft error mechanism by neutron.

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Fig. 3.  (Color online) Contribution ratio of each particle in SRAM.

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Fig. 4.  (Color online) Pulse quenching mechanism.

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Fig. 5.  CMOS cross section,showing parasitic elements.

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Fig. 6.  Schematic of the 6T1R1C hardened SRAM cell.

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Fig. 7.  DICE cell.

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Fig. 8.  11T hardened memory cell.

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Fig. 9.  13T hardened memory cell.

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Fig. 10.  (a) Critical charge plot and performance,(b) power and area comparison of the DICE,11T and 13T cells.

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Fig. 11.  MBU mitigation technique using well-slit for MBL.

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Fig. 12.  The temporal sampling latch for DSET mitigation.

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Fig. 13.  Guard-gate latch for DSET mitigation.

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Fig. 14.  (a) Current-based charge pump. (b) Voltage-based charge pump.

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Fig. 15.  The structure and hardening performance of PLL with CCL.

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Fig. 16.  $M$-path redundancy bias circuit.

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Fig. 17.  Simplified diagram of the RHBD VCO excluding the input-bias stages and current sources required to set the delay in each delay stage.

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Fig. 18.  Comparison between guard ring,guard drain and conventional layout.

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Fig. 19.  Schematic of complementary folded-cascode operational amplifier with stages labeled.

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Fig. 20.  (Color online) The three irradiated layouts of mirrored pair N9/N10 incascade stage with pre-buffered output $V_{\rm buf}$.

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Fig. 21.  (Color online) Sensitive area of the three cascade stage layouts as a function of laser energy squared.

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    Received: 11 June 2015 Revised: Online: Published: 01 November 2015

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      Article Navigation >  Journal of Semiconductors  > 2015  >  36(11): 111001
      Yuanfu Zhao, Suge Yue, Xinyuan Zhao, Shijin Lu, Qiang Bian, Liang Wang, Yongshu Sun. Single event soft error in advanced integrated circuit[J]. Journal of Semiconductors, 2015, 36(11): 111001. doi: 10.1088/1674-4926/36/11/111001 Y F Zhao, S G Yue, X Y Zhao, S J Lu, Q Bian, L Wang, Y S Sun. Single event soft error in advanced integrated circuit[J]. J. Semicond., 2015, 36(11): 111001. doi: 10.1088/1674-4926/36/11/111001.Export: BibTex EndNote
      Citation:
      Yuanfu Zhao, Suge Yue, Xinyuan Zhao, Shijin Lu, Qiang Bian, Liang Wang, Yongshu Sun. Single event soft error in advanced integrated circuit[J]. Journal of Semiconductors, 2015, 36(11): 111001. doi: 10.1088/1674-4926/36/11/111001

      Y F Zhao, S G Yue, X Y Zhao, S J Lu, Q Bian, L Wang, Y S Sun. Single event soft error in advanced integrated circuit[J]. J. Semicond., 2015, 36(11): 111001. doi: 10.1088/1674-4926/36/11/111001.
      Export: BibTex EndNote
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      Single event soft error in advanced integrated circuit

      doi: 10.1088/1674-4926/36/11/111001
      • 1.

        Beijing Microelectronics Technology Institute, Beijing 100076, China

      • 2.

        Beijing University of Aeronautics & Astronautics, Beijing 100191, China

      More Information
      • Corresponding author: Zhao Xinyuan, Email: denniso@163.com
      • Received Date: 2015-06-11
      • Accepted Date: 2015-07-23
      • Published Date: 2015-01-25

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