SEMICONDUCTOR DEVICES

Temperature effect on hetero structure junctionless tunnel FET

Shiromani Balmukund Rahi1, Bahniman Ghosh1, 2 and Bhupesh Bishnoi1

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 Corresponding author: Shiromani Balmukund Rahi, E-mail: sbrahi@gmail.com,sbrahi@iitk.ac.in

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Abstract: For the first time, we investigate the temperature effect on AlGaAs/Si based hetero-structure junctionless double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved subthreshold slope (<60 mV/decade at 300 K) and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.

Key words: TFETsubthreshold slope (SS)temperature effectband-to-band tunneling



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Fig. 1.  Cross-section of heterostructure junctionless double gate TFET (HJL-DG FET). In this structure, silicon (right) is attached to the source contact, while AlGaAs (left) is attached to the drain contact.

Fig. 2.  Band diagram of uniformly n-doped hetero structure JL-DG TFET at 300 K. (a) Equilibrium band-diagram. (b) OFF-state. (c) ON-state.

Fig. 3.  $I_{\rm D}$-$V_{\rm G}$ characteristics of HJL-DG TFET with gate voltage ranging from 0 -1.0 V for the temperature range 0-600 K at $V_{\rm DS}$ $=$ 0.35 V, $T_{\rm ox}$ $=$ 2 nm.

Fig. 4.  Screening length modulation with temperature for AlGaAs/Si based HJL- DGTFET. VB and CB stand for valance band and conduction band, respectively.

Fig. 5.  $I_{\rm ON}$-$I_{\rm OFF}$ variation with temperature for $V_{\rm DS}$ $=$ 0.35 V at 0-600 K.

Fig. 6.  $I_{\rm ON}$-$I_{\rm OFF}$ variation with temperature for $V_{\rm DS}$ $=$ 0.35 V at 300-600 K.

Fig. 7.  $I_{\rm ON}$/$I_{\rm OFF}$ ratio variation with temperature at $V_{\rm DS}$ $=$ 0.35 V for 0-600 K.

Fig. 8.  $I_{\rm ON}$/$I_{\rm OFF}$ ratio variation with temperature at $V_{\rm DS}$ $=$ 0.35 V at 300-600 K.

Fig. 9.  Subthreshold slope variation with temperature.

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Table 1.   Parameters used in simulation.

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    Received: 28 March 2014 Revised: Online: Published: 01 March 2015

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      Shiromani Balmukund Rahi, Bahniman Ghosh, Bhupesh Bishnoi. Temperature effect on hetero structure junctionless tunnel FET[J]. Journal of Semiconductors, 2015, 36(3): 034002. doi: 10.1088/1674-4926/36/3/034002 S B Rahi, B Ghosh, B Bishnoi. Temperature effect on hetero structure junctionless tunnel FET[J]. J. Semicond., 2015, 36(3): 034002. doi: 10.1088/1674-4926/36/3/034002.Export: BibTex EndNote
      Citation:
      Shiromani Balmukund Rahi, Bahniman Ghosh, Bhupesh Bishnoi. Temperature effect on hetero structure junctionless tunnel FET[J]. Journal of Semiconductors, 2015, 36(3): 034002. doi: 10.1088/1674-4926/36/3/034002

      S B Rahi, B Ghosh, B Bishnoi. Temperature effect on hetero structure junctionless tunnel FET[J]. J. Semicond., 2015, 36(3): 034002. doi: 10.1088/1674-4926/36/3/034002.
      Export: BibTex EndNote

      Temperature effect on hetero structure junctionless tunnel FET

      doi: 10.1088/1674-4926/36/3/034002
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      • Corresponding author: E-mail: sbrahi@gmail.com,sbrahi@iitk.ac.in
      • Received Date: 2014-03-28
      • Accepted Date: 2014-09-22
      • Published Date: 2015-01-25

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