SEMICONDUCTOR DEVICES

Design of high reliability RF-LDMOS by suppressing the parasitic bipolar effect using enhanced p-well and double epitaxy

Xiangming Xu1, 2, , Jingfeng Huang2, Han Yu2, Wensheng Qian2, Zhengliang Zhou2, Bo Han2, 3, Yong Wang1, Pengfei Wang1 and Zhang Wei1

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 Corresponding author: Xiangming Xu, Email: xiangming.xu@hhgrace.com

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Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) device design with an enhanced p-well and double p-epitaxial structure is investigated for device ruggedness improvement while keeping its high device performance under high frequency. Based upon the device design, radio-frequency (RF) LDMOS transistors for GSM (global system for mobile communication) application have been fabricated by using 0.35 μm CMOS technologies. Experimental data show that the proposed device achieves a breakdown voltage of 70 V, output power of 180 W. The RF linear gain is over 20 dB and the power added efficiency (PAE) is over 70% with the frequency of 920 MHz. In particular, it can pass the 20 : 1 voltage standing wave ratio (VSWR) load mismatch biased at drain DC supply voltage of 32 V and output power at 10-dB gain compression point (P10dB). The device ruggedness has been remarkably improved by using the proposed device structure.

Key words: RF powerLDMOSsemiconductor deviceruggednessreliability



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Fig. 1.  (a) Schematic of the LDMOS FET. (b) Equivalent circuit of LDMOS transistor,where a parasitic BJT is shown.

Fig. 2.  (a) Schematic of the LDMOS FET with an enhanced p-well. (b) Schematic of the proposed LDMOS device with double EPI and enhanced p-well.

Fig. 3.  The comparison of the surface electric field for transistors T1,T2,T3.

Fig. 4.  (Color online) The distribution of electric field for different LDMOS FETs when the devices are at reverse breakdown status. (a) Transistor T1. (b) Transistor T2. (c) Transistor T3.

Fig. 5.  The total current distribution for (a) transistor T2 and (b) transistor T3.

Fig. 6.  The comparison of transmission line pulse (TLP) test for transistors T1,T2,T3.

Fig. 7.  $I_{\rm d}$-$V_{\rm d}$ curve comparison of T1,T2,T3.

Fig. 8.  (a) Focus load pull system and (b) its schematic diagram.

Fig. 9.  (a) Transistor T2 passes VSWR 20 : 1 at $P_{\rm 3dB}$ output power while goes into catastrophic failure at $P_{\rm 6dB}$. (b) Transistor T3 passes VSWR 20 : 1 from $P_{\rm 3dB}$ to $P_{\rm 10dB}$ output power.

Fig. 10.  The comparisons of output power and efficiency for transistors T2,T3.

Fig. 11.  The degradation experiment for (a) conduction resistance and (b) quiescent current.

Table 1.   Three types of device simulated.

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Table 2.   The comparison of transmission line pulse (TLP) test for transistors T1,T2,T3.

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Table 3.   The comparison of ruggedness for conventional and proposed LDMOS devices.

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    Received: 16 December 2014 Revised: Online: Published: 01 June 2015

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      Xiangming Xu, Jingfeng Huang, Han Yu, Wensheng Qian, Zhengliang Zhou, Bo Han, Yong Wang, Pengfei Wang, Zhang Wei. Design of high reliability RF-LDMOS by suppressing the parasitic bipolar effect using enhanced p-well and double epitaxy[J]. Journal of Semiconductors, 2015, 36(6): 064013. doi: 10.1088/1674-4926/36/6/064013 X M Xu, J F Huang, H Yu, W S Qian, Z L Zhou, B Han, Y Wang, P F Wang, Z Wei. Design of high reliability RF-LDMOS by suppressing the parasitic bipolar effect using enhanced p-well and double epitaxy[J]. J. Semicond., 2015, 36(6): 064013. doi: 10.1088/1674-4926/36/6/064013.Export: BibTex EndNote
      Citation:
      Xiangming Xu, Jingfeng Huang, Han Yu, Wensheng Qian, Zhengliang Zhou, Bo Han, Yong Wang, Pengfei Wang, Zhang Wei. Design of high reliability RF-LDMOS by suppressing the parasitic bipolar effect using enhanced p-well and double epitaxy[J]. Journal of Semiconductors, 2015, 36(6): 064013. doi: 10.1088/1674-4926/36/6/064013

      X M Xu, J F Huang, H Yu, W S Qian, Z L Zhou, B Han, Y Wang, P F Wang, Z Wei. Design of high reliability RF-LDMOS by suppressing the parasitic bipolar effect using enhanced p-well and double epitaxy[J]. J. Semicond., 2015, 36(6): 064013. doi: 10.1088/1674-4926/36/6/064013.
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      Design of high reliability RF-LDMOS by suppressing the parasitic bipolar effect using enhanced p-well and double epitaxy

      doi: 10.1088/1674-4926/36/6/064013
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      Project supported by the Chinese National Key Project (No. 2012ZX02502).

      More Information
      • Corresponding author: Email: xiangming.xu@hhgrace.com
      • Received Date: 2014-12-16
      • Accepted Date: 2015-01-21
      • Published Date: 2015-01-25

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