SEMICONDUCTOR INTEGRATED CIRCUITS

An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient

Vinayak Hande and Maryam Shojaei Baghini

+ Author Affiliations

 Corresponding author: Vinayak Hande, vinayak.hande@iitb.ac.in; Shojaei Baghini, mshojaei@ee.iitb.ac.in

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Abstract: A novel current-mode voltage reference circuit which is capable of generating sub-1 V output voltage is presented. The proposed architecture exhibits the inherent curvature compensation ability. The curvature compensation is achieved by utilizing the non-linear behavior of gate coupling coefficient to compensate non-linear temperature dependence of base-emitter voltage. We have also utilized the developments in CMOS process to reduce power and area consumption. The proposed voltage reference is analyzed theoretically and compared with other existing methods. The circuit is designed and simulated in 180 nm mixed-mode CMOS UMC technology which gives a reference level of 246 mV. The minimum required supply voltage is 1 V with maximum current drawn of 9.24 μA. A temperature coefficient of 9 ppm/℃ is achieved over -25 to 125 ℃ temperature range. The reference voltage varies by ±11 mV across process corners. The reference circuit shows the line sensitivity of 0.9 mV/V with area consumption of 100 × 110 μm2.

Key words: voltage referencegate coupling coefficienttemperature coefficientcurvature compensation



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Fig. 1.  (a) $V_{\rm CTAT}$ i.e. $V_{\rm BE}$ as a function of temperature. (b) Scaled $V_{\rm PTAT}$ i.e. $Δ V_{\rm BE}$ as a function of temperature. (c) Reference voltage as a function of temperature. (d) Derivative of $V_{\rm CTAT}$ as a function of temperature. (e) Derivative of $V_{\rm PTAT}$ as a function of temperature. (f) Derivative of reference voltage as a function of temperature.

Figure 1


Fig. 2.  (a) Targeted derivative of reference voltage as a function of temperature. (b) Targeted derivative of scaled $V_{\rm PTAT}$ as a function of temperature. (c) Derivative of $V_{\rm CTAT}$ as a function of temperature. (d) Targeted reference voltage as a function of temperature. (e) Scaled $V_{\rm PTAT}$ as a function of temperature. (f) $V_{\rm CTAT}$ as a function of temperature.

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Fig. 3.  (a) NMOS transistor structure in the width direction for step transition isolation. (b) Variation in the $\eta$ with varying temperature for different widths.

Figure 3


Fig. 4.  (a) $V_{\rm GS}$ voltage varying with temperature. (b) Derivative of $V_{\rm GS}$ voltage varying with temperature.

Figure 4


Fig. 5.  (a) PTAT voltage varying with temperature. (b) Derivative of PTAT voltage varying with temperature.

Figure 5


Fig. 6.  Schematic of the proposed CMOS voltage reference architecture.

Figure 6


Fig. 7.  (a) Schematic of test set-up to simulate stability of the CTAT current generator loop. (b) Schematic of the single stage op-amp used in the current loop.

Figure 7


Fig. 8.  (a) Frequency response for CTAT loop. (b) Frequency response for PTAT loop.

Figure 8


Fig. 9.  Layout of the proposed voltage reference circuit.

Figure 9


Fig. 10.  (a) Reference voltage with varying temperature. (b) Reference voltage with varying supply voltage.

Figure 10


Fig. 11.  (a) Reference voltage with varying temperature across process corners. (b) PSNA of the proposed voltage reference circuit with and without filtering capacitor i.e. $C_{\rm Filter}$.

Figure 11


Fig. 12.  Noise spectrum of the proposed voltage reference at 50 ℃ with a 1 V supply.

Figure 12


Fig. 13.  Statistical representation of reference voltage for (a) process variations and (b) mismatch variations.

Figure 13


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Table 1.   Performance comparison.

Table 1

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    Received: 12 January 2015 Revised: Online: Published: 01 August 2015

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      Vinayak Hande, Maryam Shojaei Baghini. An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient[J]. Journal of Semiconductors, 2015, 36(8): 085001. doi: 10.1088/1674-4926/36/8/085001 Vinayak Hande, M S Baghini. An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient[J]. J. Semicond., 2015, 36(8): 085001. doi: 10.1088/1674-4926/36/8/085001.Export: BibTex EndNote
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      Vinayak Hande, Maryam Shojaei Baghini. An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient[J]. Journal of Semiconductors, 2015, 36(8): 085001. doi: 10.1088/1674-4926/36/8/085001

      Vinayak Hande, M S Baghini. An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient[J]. J. Semicond., 2015, 36(8): 085001. doi: 10.1088/1674-4926/36/8/085001.
      Export: BibTex EndNote

      An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient

      doi: 10.1088/1674-4926/36/8/085001
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      • Corresponding author: Vinayak Hande, vinayak.hande@iitb.ac.in; Shojaei Baghini, mshojaei@ee.iitb.ac.in
      • Received Date: 2015-01-12
      • Accepted Date: 2015-03-18
      • Published Date: 2015-01-25

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