SEMICONDUCTOR INTEGRATED CIRCUITS

An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs

Qiang Yao1, Zuochang Ye1 and Wenjian Yu2,

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 Corresponding author: Wenjian Yu, Emailyu-wj@tsinghua.edu.cn

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Abstract: To build an accurate electric model for through-silicon vias (TSVs) in 3D integrated circuits (ICs), a resistance and capacitance (RC) circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys's Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from 10 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.

Key words: 3D ICthrough silicon via (TSV)parasitic extractionfloating random walk algorithmmetal-oxide-semiconductor (MOS) capacitance



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Fig1.  Cross-section view of TSVs and conventional interconnect wires in a 3D IC.

.  A structure with one TSV. (a) The cross-section view. (b) The top view.

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Fig3.  The result comparison of the analytical method and the Sdevice simulation method.

Fig4.  The floating random walks for potential and capacitance calculations.

Fig5.  A Manhattan transition cube compared to a rotated transition cube.

Fig6.  A two-TSV structure.

Fig7.  A 5-TSV structure. (a) Top view. (b) The equivalent circuit model.

Fig8.  Results comparison on 2-TSV model.

Fig9.  Results comparison on 5-TSV model.

Fig10.  Results comparison on 9-TSV model.

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Table 1.   Geometry parameters and doping concentration for the test case with one TSV.

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Table 2.  

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Table 3.  

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Table 4.   Runtime comparison of proposed method and Sdevice.

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    Received: 01 February 2015 Revised: Online: Published: 01 August 2015

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      Qiang Yao, Zuochang Ye, Wenjian Yu. An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs[J]. Journal of Semiconductors, 2015, 36(8): 085006. doi: 10.1088/1674-4926/36/8/085006 Q Yao, Z C Ye, W J Yu. An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs[J]. J. Semicond., 2015, 36(8): 085006. doi: 10.1088/1674-4926/36/8/085006.Export: BibTex EndNote
      Citation:
      Qiang Yao, Zuochang Ye, Wenjian Yu. An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs[J]. Journal of Semiconductors, 2015, 36(8): 085006. doi: 10.1088/1674-4926/36/8/085006

      Q Yao, Z C Ye, W J Yu. An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs[J]. J. Semicond., 2015, 36(8): 085006. doi: 10.1088/1674-4926/36/8/085006.
      Export: BibTex EndNote

      An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs

      doi: 10.1088/1674-4926/36/8/085006
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      Project supported by the National Natural Science Foundation of China (No. 61422402), and the Tsinghua University Initiative Scientific Research Program.

      More Information
      • Corresponding author: Emailyu-wj@tsinghua.edu.cn
      • Received Date: 2015-02-01
      • Accepted Date: 2015-03-11
      • Published Date: 2015-01-25

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