SEMICONDUCTOR INTEGRATED CIRCUITS

A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background

Xiaofei Wang1, , Hong Zhang2, Jie Zhang2, Xin Du2 and Yue Hao1

+ Author Affiliations

 Corresponding author: Wang Xiaofei, Email:xjtuwxf@126.com

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Abstract: A 14-bit 100-MS/s pipelined analog-to-digital converter(ADC) without dedicated front-end sample-and-hold amplifier(SHA) is presented. In addition to elaborate matching of the sampling network in the first stage, a background offset cancellation circuit is proposed in this paper to suppress the offset of the comparators in the first-stage sub-ADC, which ensures the overall offset does not exceed the correction range of the built-in redundant structure. Fabricated in a 0.18-μm CMOS technology, the presented ADC occupies a chip area of 12 mm2, and consumes 237 mW from a 1.8-V power supply. Measurement results with a 30.1-MHz input sine wave under a sampling rate of 100 MS/s show that the ADC achieves a 71-dB signal-to-noise and distortion ratio(SNDR), an 85.4-dB spurious-free dynamic range(SFDR), a maximum differential nonlinearity(DNL) of 0.22 LSB and a maximum integral nonlinearity(INL) of 1.4 LSB.

Key words: SHA-lesspipelined ADCclock skewcomparator offsetbackground



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Fig1.  Architecture of the presented ADC.

Fig2.  The 3-bit first stage. (a) Conceptual structure. (b) Timing of the control clock signals. (c) Impact of the sampling clock skew.

Fig3.  Residue voltage transfer curve with effect of comparator offset and clock skew for the 3-bit first stage.

Fig4.  Proposed comparator with background offset cancellation. (a) Schematic. (b) Control timing.

Fig5.  Simulated offset cancellation results of the proposed comparator with (a) 10 mV and (b) -10 mV RTI offset.

Fig6.  Simplified schematic of the first-stage residue amplifier.

Fig7.  Simulated residue curve of the first stage without clock skew and comparator offset.

Fig8.  (Color online) Chip photo of the presented ADC.

Fig9.  Measured spectrum with a 30.1 MHz sine input under sampling rate of 100 MS/s. (a) Offset cancellation turned off. (b) Offset cancellation turned on.

Fig10.  Measured (a) DNL and (b) INL.

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Table 1.   Performance summary and comparison.

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    Received: 25 July 2015 Revised: Online: Published: 01 March 2016

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      Xiaofei Wang, Hong Zhang, Jie Zhang, Xin Du, Yue Hao. A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background[J]. Journal of Semiconductors, 2016, 37(3): 035002. doi: 10.1088/1674-4926/37/3/035002 X F Wang, H Zhang, J Zhang, X Du, Y Hao. A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background[J]. J. Semicond., 2016, 37(3): 035002. doi: 10.1088/1674-4926/37/3/035002.Export: BibTex EndNote
      Citation:
      Xiaofei Wang, Hong Zhang, Jie Zhang, Xin Du, Yue Hao. A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background[J]. Journal of Semiconductors, 2016, 37(3): 035002. doi: 10.1088/1674-4926/37/3/035002

      X F Wang, H Zhang, J Zhang, X Du, Y Hao. A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background[J]. J. Semicond., 2016, 37(3): 035002. doi: 10.1088/1674-4926/37/3/035002.
      Export: BibTex EndNote

      A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background

      doi: 10.1088/1674-4926/37/3/035002
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      Project supported by the National Natural Science Foundation of China(No.61474092).

      More Information
      • Corresponding author: Wang Xiaofei, Email:xjtuwxf@126.com
      • Received Date: 2015-07-25
      • Accepted Date: 2015-09-07
      • Published Date: 2016-01-25

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