SEMICONDUCTOR DEVICES

Performance analysis of charge plasma based dual electrode tunnel FET

Sunny Anand, S. Intekhab Amin and R. K. Sarin

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 Corresponding author: Sunny Anand, Email: sunnyanand.ec.13@nitj.ac.in

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Abstract: This paper proposes the charge plasma based dual electrode doping-less tunnel FET (DEDLTFET). The paper compares the device performance of the conventional doping-less TFET (DLTFET) and doped TFET (DGTFET). DEDLTEFT gives the superior results with high ON state current (ION ~ 0.56 mA/μm), ION/IOFF ratio ~ 9.12 × 1013 and an average subthreshold swing (AV-SS ~ 48 mV/dec). The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.

Key words: band to band tunneling (BTBT)charge plasmadoping-less tunnel field effect transistor (DLTFET)average subthreshold swingdrain induced barrier lowering (DIBL)



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Fig. 1.  Schematic cross sectional view of (a) conventional doped DGTFE [6], (b) conventional DLTFETŒ[12] and (c) DEDLTFET.

Fig. 2.  Drain current characteristics between reported DLTFETŒ[12], calibrated DLTFET and DEDLTEFT at VDS D 1.0 V.

Fig. 3.  (Color online) Contour plot of (a) electron, (b) hole carrier concentrations for DLTFET and (c) electron, (d) hole concentrations for DEDLTFET at VGS= D VDS = 1.0 V.

Fig. 4.  (Color online) Electric field profile in the DEDLTEFT, DLTFET and DGTFET at OFF state (VDS = 1.0 V, VGS = 0.0 V) and ON state (VDS= VGS = 1.0 V).

Fig. 5.  Energy band diagram of (a) DEDLTFET near the front gate and (b) DEDLTFET, DLTFET and DG-TFET near the back gate (VGS = VDS = 1.0 V).

Fig. 6.  Band to band tunneling rate for electrons of DEDLTFET, DLTFET and DG-TFET (a) near the front gate and (b) near the back gate (VGS = VDS = 1.0 V).

Fig7.  Drain current to gate voltage characteristics between DGTFET, DLTFET and DEDLTEFT at VDS = 1.0 V.

Fig. 8.  DIBL effects in (a) DEDLTFET, (b) DLTFET, and (c) DGTFET.

Fig. 9.  Average subthreshold slope and threshold voltage as a function of the different dielectric constant for DEDLTFET, DLTFET, and DGTFET with Lg = 50 nm, tox = 2 nm, tsi = 10 nm.

Fig. 10.  Drain induced barrier lowering (DIBL) and ION=IOFF ratio as a function of different dielectric constants for DEDLTFET, DLTFET, and DGTFET.

Fig. 11.  (a) ON state current and average subthreshold slope and (b) ION=IOFF ratio and threshold voltage as function of different gate oxide thickness for DEDLTFET, DLTFET, and DGTFET

Fig. 12.  Average subthreshold slope and ON state current as function of different gate work function for DEDLTFET,DLTFET,and DGTFET.

Fig. 13.  DIBL and threshold voltage as function of varying work function for DEDLTFET,DLTFET,and DGTFET.

Fig. 14.  ON state and OFF state current for different gate length for DEDLTFET,DLTFET,and DGTFET.

Fig. 15.  $I_{\rm ON}/I_{\rm OFF}$ ratio and threshold voltage for different gate length for DEDLTFET,DLTFET,and DGTFET.

Fig. 16.  $I_{\rm ON}/I_{\rm OFF}$ ratio and DIBL as a function of silicon thickness for DEDLTFET,DLTFET,and DGTFET.

Fig. 17.  ON state current and $I_{\rm ON}/I_{\rm OFF}$ ratio as a function of temperature for DEDLTFET,DLTFET,and DGTFET.

Fig. 18.  Threshold voltage ($V_{\rm T})$ and average subthreshold swing as a function of temperature for DEDLTFET,DLTFET,and DGTFET.

Table 1.   Parameters used for DG-TFET, DLTFET and DEDLTFET

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    Received: 12 August 2015 Revised: Online: Published: 01 May 2016

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      Sunny Anand, S. Intekhab Amin, R. K. Sarin. Performance analysis of charge plasma based dual electrode tunnel FET[J]. Journal of Semiconductors, 2016, 37(5): 054003. doi: 10.1088/1674-4926/37/5/054003 S Anand, S. I. Amin, R. K. Sarin. Performance analysis of charge plasma based dual electrode tunnel FET[J]. J. Semicond., 2016, 37(5): 054003. doi:  10.1088/1674-4926/37/5/054003.Export: BibTex EndNote
      Citation:
      Sunny Anand, S. Intekhab Amin, R. K. Sarin. Performance analysis of charge plasma based dual electrode tunnel FET[J]. Journal of Semiconductors, 2016, 37(5): 054003. doi: 10.1088/1674-4926/37/5/054003

      S Anand, S. I. Amin, R. K. Sarin. Performance analysis of charge plasma based dual electrode tunnel FET[J]. J. Semicond., 2016, 37(5): 054003. doi:  10.1088/1674-4926/37/5/054003.
      Export: BibTex EndNote

      Performance analysis of charge plasma based dual electrode tunnel FET

      doi: 10.1088/1674-4926/37/5/054003
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      • Corresponding author: Email: sunnyanand.ec.13@nitj.ac.in
      • Received Date: 2015-08-12
      • Accepted Date: 2015-09-24
      • Published Date: 2016-01-25

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