SEMICONDUCTOR INTEGRATED CIRCUITS

A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE

Xuemin Li, Mao Ye, Gongyuan Zhao, Yun Zhang and Yiqiang Zhao

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 Corresponding author: Corresponding author. Email: nkyemao@163.com

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Abstract: A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage |VGS|p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages |VGS|n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages ΔVBE of bipolar junction transistors (BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm/℃ without trimming, over a temperature range from -40 to 120 ℃, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio (PSRR) is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2.

Key words: voltage referencesub-referencecurvature compensationsubthreshold



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Fig1.  Basic architecture of the proposed reference.

Fig2.  Variation of $\vert V_{\rm GS} \vert_{\rm p}-f$ with temperature under different $e$ values.

Fig3.  (Color online) Simulated results of temperature characteristics of the first second sub-references and output voltage reference.

Fig4.  Proposed solution for the reference architecture.

Fig5.  (a) Current generator used in the voltage reference. (b) Current generator for low power supply application.

Fig6.  The operational amplifier used in the voltage reference.

Fig7.  (Color online) Chip micrograph.

Fig8.  Measured temperature dependence of the proposed reference.

Fig9.  Measured PSRR at room temperature.

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Table 1.   Measured temperature dependence of 6 different samples.

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Table 2.   Comparison of the proposed reference with prior art design.

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    Received: 25 August 2015 Revised: Online: Published: 01 May 2016

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      Xuemin Li, Mao Ye, Gongyuan Zhao, Yun Zhang, Yiqiang Zhao. A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE[J]. Journal of Semiconductors, 2016, 37(5): 055005. doi: 10.1088/1674-4926/37/5/055005 X M Li, M Ye, G Y Zhao, Y Zhang, Y Q Zhao. A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE[J]. J. Semicond., 2016, 37(5): 055005. doi: 10.1088/1674-4926/37/5/055005.Export: BibTex EndNote
      Citation:
      Xuemin Li, Mao Ye, Gongyuan Zhao, Yun Zhang, Yiqiang Zhao. A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE[J]. Journal of Semiconductors, 2016, 37(5): 055005. doi: 10.1088/1674-4926/37/5/055005

      X M Li, M Ye, G Y Zhao, Y Zhang, Y Q Zhao. A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE[J]. J. Semicond., 2016, 37(5): 055005. doi: 10.1088/1674-4926/37/5/055005.
      Export: BibTex EndNote

      A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE

      doi: 10.1088/1674-4926/37/5/055005
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      Project supported by the National Natural Science Foundation of China (No. 61376032).

      More Information
      • Corresponding author: Corresponding author. Email: nkyemao@163.com
      • Received Date: 2015-08-25
      • Accepted Date: 2015-10-12
      • Published Date: 2016-01-25

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