SEMICONDUCTOR INTEGRATED CIRCUITS

A load balancing bufferless deflection router for network-on-chip

Xiaofeng Zhou, Zhangming Zhu and Duan Zhou

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 Corresponding author: Zhou Xiaofeng, Email: zhouxiaofeng04140@163.com

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Abstract: The bufferless router emerges as an interesting option for cost-efficient in network-on-chip (NoC) design. However, the bufferless router only works well under low network load because deflection more easily occurs as the injection rate increases. In this paper, we propose a load balancing bufferless deflection router (LBBDR) for NoC that relieves the effect of deflection in bufferless NoC. The proposed LBBDR employs a balance toggle identifier in the source router to control the initial routing direction of X or Y for a flit in the network. Based on this mechanism, the flit is routed according to XY or YX routing in the network afterward. When two or more flits contend the same one desired output port a priority policy called nearer-first is used to address output ports allocation contention. Simulation results show that the proposed LBBDR yields an improvement of routing performance over the reported bufferless routing in the flit deflection rate, average packet latency and throughput by up to 13%, 10% and 6% respectively. The layout area and power consumption compared with the reported schemes are 12% and 7% less respectively.

Key words: NoCload balancingdeflection router



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.  Architecture for baseline deflection router.

.  Architecture for LDBR.

.  Architecture for LBBDR.

.  (Color online) Routing paths of BBDR, LDBR and LBBDR. (a) Routing paths of XY routing. (b) Routing paths of load balancing deflection routing.

.  (Color online) Port contention of BBDR, LDBR and LBBDR. (a) Ports contention of XY routing. (b) Ports contention of load balancing deflection routing.

.  Deflection rate under two traffic patterns. (a) Random traffic pattern with 4 $\times$ 4 mesh. (b) Random traffic pattern with 8 $\times$ 8 mesh. (c) Transpose traffic pattern with 4 $\times$ 4 mesh. (d) Transpose traffic pattern with 8 $\times$ 8 mesh.

.  Average latency under two traffic patterns. (a) Random traffic pattern with 4 $\times$ 4 mesh. (b) Random traffic pattern with 8 $\times$ 8 mesh. (c) Transpose traffic pattern with 4 $\times$ 4 mesh. (d) Transpose traffic pattern with 8 $\times$ 8 mesh.

.  Throughput under two traffic patterns. (a) Random traffic pattern with 4 $\times$ 4 mesh. (b) Random traffic pattern with 8 $\times$ 8 mesh. (c) Transpose traffic pattern with 4 $\times$ 4 mesh. (d) Transpose traffic pattern with 8 $\times$ 8 mesh.

.  (Color online) Layout area and power consumption. (a) Layout area for different size network. (b) Power consumption for different size network.

.   Timing critical path (ps).

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    Received: 15 October 2015 Revised: Online: Published: 01 July 2016

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      Xiaofeng Zhou, Zhangming Zhu, Duan Zhou. A load balancing bufferless deflection router for network-on-chip[J]. Journal of Semiconductors, 2016, 37(7): 075002. doi: 10.1088/1674-4926/37/7/075002 X F Zhou, Z M Zhu, D Zhou. A load balancing bufferless deflection router for network-on-chip[J]. J. Semicond., 2016, 37(7): 075002. doi: 10.1088/1674-4926/37/7/075002.Export: BibTex EndNote
      Citation:
      Xiaofeng Zhou, Zhangming Zhu, Duan Zhou. A load balancing bufferless deflection router for network-on-chip[J]. Journal of Semiconductors, 2016, 37(7): 075002. doi: 10.1088/1674-4926/37/7/075002

      X F Zhou, Z M Zhu, D Zhou. A load balancing bufferless deflection router for network-on-chip[J]. J. Semicond., 2016, 37(7): 075002. doi: 10.1088/1674-4926/37/7/075002.
      Export: BibTex EndNote

      A load balancing bufferless deflection router for network-on-chip

      doi: 10.1088/1674-4926/37/7/075002
      More Information
      • Corresponding author: Zhou Xiaofeng, Email: zhouxiaofeng04140@163.com
      • Received Date: 2015-10-15
      • Accepted Date: 2016-01-04
      • Published Date: 2016-07-25

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