Fig. 1.
Architecture of subrange SAR ADC
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Xiuju He, Xian Gu, Weitao Li, Hanjun Jiang, Fule Li, Zhihua Wang. An 11-bit 200 MS/s subrange SAR ADC with low-cost integrated reference buffer[J]. Journal of Semiconductors, 2017, 38(10): 105007. doi: 10.1088/1674-4926/38/10/105007
X J He, X Gu, W T Li, H J Jiang, F L Li, Z H Wang. An 11-bit 200 MS/s subrange SAR ADC with low-cost integrated reference buffer[J]. J. Semicond., 2017, 38(10): 105007. doi: 10.1088/1674-4926/38/10/105007.
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An 11-bit 200 MS/s subrange SAR ADC with low-cost integrated reference buffer
doi: 10.1088/1674-4926/38/10/105007
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Abstract
This paper presents an 11-bit 200 MS/s subrange SAR ADC with an integrated reference buffer in 65 nm CMOS. The proposed ADC employs a 3.5-bit flash ADC for coarse conversion, and a compact timing scheme at the flash/SAR boundary to speed up the conversion. The flash decision is used to control charge compensating for the reference voltage to reduce its input-dependent fluctuation. Measurement results show that the fabricated ADC has achieved significant improvement by applying the reference charge compensation. In addition, the ADC achieves a maximum signal-to-noise-and-distortion ratio of 59.3 dB at 200 MS/s. It consumes 3.91 mW from a 1.2 V supply, including the reference buffer. -
References
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