SEMICONDUCTOR TECHNOLOGY

Method to remove wafer surface particles

Bo Peng, Deguang Zheng and Yue Yu

+ Author Affiliations

 Corresponding author: Deguang Zheng Email: deane.zheng@nxp.com

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Abstract: A big yield drop has been observed during the automatic inspection (AOI) after the saw stage. A step by step AOI inspection check and defect review is made to see which step made a big yield drop and which kind of defect contributed most to the yield drop. Scanning electron microscope (SEM) and energy dispersive spectrometer (EDS) analysis showed the shape and chemical element of the particle. From the EDS result, particles can be separated into two categories. One was the inorganic related materials, mainly including silicon (Si) element, which came from the saw stage. A design of experiment (DOE) is used to find some reasonable saw relative parameter and optimize it in order to remove the particle from the saw stage. But the quantity of this kind of particle was small. Yield was only improved by less than 5%. Our main effort was to remove another kind of particle which was organic related materials, mainly including carbon (C) and oxygen (O) element. This kind of particle was from tape residue. In order to remove the tape residual, one step was added before the saw stage. Almost all of the tape residual was removed. Finally, the final yield was improved by more than 15%.

Key words: yielddefectwafer



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Seo Y J, Kim S Y, Lee W S. Advantages of point of use (POU) slurry filter and high spray method for reduction of CMP process defects. Microelectron Eng, 2003, 70:1 doi: 10.1016/S0167-9317(03)00278-8
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Ahn Y, Yoon J Y, Baek C W, et al. Chemical mechanical polishing by colloidal silica-based slurry for micro-scratch reduction. Wear, 2004, 257(7):785 http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.418.8323
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Fig. 1.  Standard process flow

Fig. 2.  Particle image under microscope 50×

Fig. 3.  SEM and EDS analysis on inorganic particle

Fig. 4.  SEM and EDS analysis on organic particle

Fig. 5.  Wafer yield before process optimized (75.52%)

Fig. 6.  Wafer yield after process optimized (86.71%)

Table 1.   DOE to find optimize saw parameter

Table 2.   Using short UV time on the backside of the wafer

Table 3.   Using different tape

Table 4.   Top side UV with different speeds

[1]
Shimizu M, Ishii A, Nishimura T. Detection of foreign material included in LCD panels. 26th Annual Conference of the IEEE, 2000, 2:836 http://www.academia.edu/3452902/Study_on_Various_Glass_Defect_Using_Glass_Edge_Detection_Methods_
[2]
Bhattacharyya D, Hong W, Peng K, et al. Reduction of extra pattern defects in immersion layer reworks by cleans recipe optimization:CFM:Contamination free manufacturing. 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2016, 1:229 http://smtnet.com/index.cfm?fuseaction=search_submit&searchstring=solder%20wire%20&collection=full_site
[3]
Shim S, Chung W, Shin Y. Lithography defect probability and its application to physical design optimization. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2017, 25(1):271 doi: 10.1109/TVLSI.2016.2572224
[4]
Johnson M, Noble B, Johnson M, et al. Active reliability monitor:defect level extrinsic reliability monitoring on 22 nm POWER8 and zSeries processors. IEEE International Test Conference (ITC), 2016, 1:1 http://www.freepatentsonline.com/y2006/0235842.html
[5]
Dau S M, Hun O S, Chin C C, et al. Photoresist residue defect by etch byproduct on PIP etch process. IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 2015, 1:1 http://www.sciencedirect.com/science/article/pii/B9780323299619000053
[6]
Funahashi T, Taki K, Koshimizu H, et al. Fast and robust visual inspection system for tire surface thin defect. 21st Korea-Japan Joint Workshop on Frontiers of Computer Vision (FCV), 2015, 1:1 doi: 10.1007/978-3-319-33618-3_8
[7]
Liu Y L, Sie W S, Chen C L, et al. Defect reduction with CMP pad dressing optimization. Proceedings of International Conference on Planarization/CMP Technology, 2014, 1:330 https://www.deepdyve.com/lp/institute-of-electrical-and-electronics-engineers/defect-reduction-with-cmp-pad-dressing-optimization-q5x5fghEFv
[8]
Chen N, Jiang L, Yu F, et al. Failure analysis of foreign materials in electronic packaging assembly. High Density Microsystem Design and Packaging and Component Failure Analysis, 2005, 1:1 http://focus.ti.com/en/download/qlty/SEMICONDUCTOR_PACKAGING_ASSEMBLY_TECHNOLOGY-MISC.pdf
[9]
Seo Y J, Kim S Y, Lee W S. Advantages of point of use (POU) slurry filter and high spray method for reduction of CMP process defects. Microelectron Eng, 2003, 70:1 doi: 10.1016/S0167-9317(03)00278-8
[10]
Ahn Y, Yoon J Y, Baek C W, et al. Chemical mechanical polishing by colloidal silica-based slurry for micro-scratch reduction. Wear, 2004, 257(7):785 http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.418.8323
[11]
Kim D H, Kang H G, Kim S K, et al. Agglomerated large particles under various slurry preparation conditions and their influence on shallow trench isolation chemical mechanical polishing. Jpn J Appl Phys, Part 1, 2005, 44(11):7770 doi: 10.1143/JJAP.44.7770
[12]
Chang F C, Singh R K. Method for quantifying the degree of agglomeration in highly stable chemical mechanical polishing slurries. Electrochem Solid-State Lett, 2009, 12(4):127 doi: 10.1149/1.3074306
[13]
Hsien Y H, Hsu H K, Tsai T C, et al. Process development of high-k metal gate aluminum CMP at 28 nm technology node. Microelectron Eng, 2012, 92:19 doi: 10.1016/j.mee.2011.04.013
[14]
Prasad Y N, Kwon T Y, Kim I K, et al. Generation of pad debris during oxide CMP process and Its role in scratch formation. J Electrochem Soc, 2011, 158(4):394 doi: 10.1007/s40544-013-0026-y
[15]
Kwon T Y, Cho B J, Ramachandran M, et al. Investigation of source-based scratch formation during oxide chemical mechanical planarization. Tribol Lett, 2013, 50(2):169 doi: 10.1007/s11249-012-0098-2
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    Received: 20 January 2017 Revised: 05 April 2017 Online: Published: 01 September 2017

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      Bo Peng, Deguang Zheng, Yue Yu. Method to remove wafer surface particles[J]. Journal of Semiconductors, 2017, 38(9): 096004. doi: 10.1088/1674-4926/38/9/096004 B Peng, D G Zheng, Y Yu. Method to remove wafer surface particles[J]. J. Semicond., 2017, 38(9): 096004. doi: 10.1088/1674-4926/38/9/096004.Export: BibTex EndNote
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      Bo Peng, Deguang Zheng, Yue Yu. Method to remove wafer surface particles[J]. Journal of Semiconductors, 2017, 38(9): 096004. doi: 10.1088/1674-4926/38/9/096004

      B Peng, D G Zheng, Y Yu. Method to remove wafer surface particles[J]. J. Semicond., 2017, 38(9): 096004. doi: 10.1088/1674-4926/38/9/096004.
      Export: BibTex EndNote

      Method to remove wafer surface particles

      doi: 10.1088/1674-4926/38/9/096004
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      • Corresponding author: Deguang Zheng Email: deane.zheng@nxp.com
      • Received Date: 2017-01-20
      • Revised Date: 2017-04-05
      • Published Date: 2017-09-01

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