Fig. 1.
The proposed equalizer architecture.
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Hongbing Wu, Jingyu Wang, Hongxia Liu. A 5 Gb/s CMOS adaptive equalizer for serial link[J]. Journal of Semiconductors, 2018, 39(4): 045003. doi: 10.1088/1674-4926/39/4/045003
H B Wu, J Y Wang, H X Liu. A 5 Gb/s CMOS adaptive equalizer for serial link[J]. J. Semicond., 2018, 39(4): 045003. doi: 10.1088/1674-4926/39/4/045003.
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A 5 Gb/s CMOS adaptive equalizer for serial link
doi: 10.1088/1674-4926/39/4/045003
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Abstract
A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13 μm CMOS process. The circuit consists of the combination of equalizer amplifier, limiter amplifier and adaptation loop. The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics. In addition, an offset cancellation loop is used to alleviate the offset influence of the signal path. The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply. Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter. -
References
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