SEMICONDUCTOR INTEGRATED CIRCUITS

Frequency equation for the submicron CMOS ring oscillator using the first order characterization

Aravinda Koithyar and T. K. Ramesh

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 Corresponding author: Aravinda Koithyar, Email: aravindak@newhorizonindia.edu

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Abstract: By utilizing the first order behavior of the device, an equation for the frequency of operation of the submicron CMOS ring oscillator is presented. A 5-stage ring oscillator is utilized as the initial design, with different Beta ratios, for the computation of the operating frequency. Later on, the circuit simulation is performed from 5-stage till 23-stage, with the range of oscillating frequency being 3.0817 and 0.6705 GHz respectively. It is noted that the output frequency is inversely proportional to the square of the device length, and when the value of Beta ratio is used as 2.3, a difference of 3.64% is observed on an average, in between the computed and the simulated values of frequency. As an outcome, the derived equation can be utilized, with the inclusion of an empirical constant in general, for arriving at the ring oscillator circuit’s output frequency.

Key words: ring oscillatorstage delaySPICE modelRC modelsecond order effects



[1]
Chebli R, Zhao X, Sawan M. A wide tuning range voltage-controlled ring oscillator dedicated to ultrasound transmitter. IEEE 16th International Conference on Microelectronics, 2004: 313 doi: 10.1109/ICM.2004.1434276
[2]
Eken Y A, Uyemura J P. A 5.9-GHz voltage-controlled ring oscillator in 0.18-μm CMOS. J Solid-State Circuits, 2004, 39: 230 doi: 10.1109/JSSC.2003.820869
[3]
Kang S M, Leblebici Y. CMOS digital integrated circuits: analysis and design. 3rd ed. McGraw-Hill Higher Education, 2002: 239
[4]
Retdian N, Takagi S, Fujii N. Voltage controlled ring oscillator with wide tuning range and fast voltage swing. IEEE Asia-Pacific Conference on ASIC, Tokyo, Japan, 2002
[5]
Jovanovic G, Stojcev M, Stamenkovic Z. A CMOS voltage controlled ring oscillator with improved frequency stability. Sci Pub State Univ Novi Pazar A, 2010, 2: 1
[6]
Rabaey J M, Chandrakasan A, Nikolic B. Digital integrated circuits – a design perspective. 2nd ed. Pearson Eduction, 2003: 194
[7]
Baker R J. CMOS: circuit design, layout, and simulation. 3rd ed. Wiley-IEEE Press, 2010: 337
[8]
Rout P K, Acharya D P. Design of CMOS ring oscillator using CMODE. IEEE International Conference on Energy, Automation, and Signal, 2011: 1
[9]
Mishra A, Sharma G K, Boolchandani D. Performance analysis of power optimal PLL design using five-stage CS-VCO in 180 nm. IEEE International Conference on Signal Propagation and Computer Technology, 2014: 764
[10]
Paydavosi N, Morshed T H, Lu D D, et al. BSIM4v4.8.0 MOSFET model - user’s manual. University of California, Berkeley, 2013
[11]
Yeo K S, Rofail S S, Goh W L. CMOS/BiCMOS ULSI. Pearson Education, 2002: 207
[12]
Farahabadi P M, Miar-Naimi H, Ebrahimzadeh A. Closed-form analytical equations for amplitude and frequency of high-frequency CMOS ring oscillators. IEEE Trans Circuits Syst I, 2009, 56: 2669 doi: 10.1109/TCSI.2009.2016179
[13]
Razavi B. Design of analog CMOS integrated circuits. 2nd Ed. McGraw Hill Education, 2001: 30
[14]
Weste N, Harris D. CMOS VLSI design: a circuits and systems perspective. 4th ed. Pearson Education, 2011
[15]
Uyemura J P. CMOS logic circuit design. Kluwer Academic Publishers, 2002: 21
[16]
Bhushan M, Ketchen M B. CMOS test and evaluation: a physical perspective. Springer, 2014: 381
[17]
Cheng Y, Hu C. MOSFET modeling and BSIM3 user’s guide. Kluwer Academic Publishers, 2002
[18]
Koithyar A, Ramesh T K. Analysis of deadbeat control for an integer-N charge-pump PLL. Proc Comput Sci, 21015, 70C, 2015, 70: 392
[19]
Koithyar A, Ramesh T K. Characterization of submicron ring oscillator using the first order design equations. IEEE International Conference on Communication and Signal Processing, 2016: 1227
Fig. 1.  Gate level diagram of 3-stage ring oscillator.

Fig. 2.  Circuit diagram of 3-stage CMOS ring oscillator.

Fig. 3.  RC model of 3-stage CMOS ring oscillator.

Fig. 4.  5-stage ring oscillator’s schematic diagram.

Fig. 5.  5-stage ring oscillator’s output waveform.

Fig. 6.  (Color online) Beta ratio versus frequency of 5-stage ring oscillator.

Fig. 7.  (Color online) Plot of computed versus simulated frequencies for different stages.

Table 1.   Frequency values with variation in B (with N = 5).

Sl. no. Wn (μm) B Wp (μm) Beta ratio (normalized) fosc (GHz)
(computed)
fosc (GHz)
(simulated)
Deviation (%)
01 0.80 1.0 0.80 1.00 3.1941 3.2776 −2.61
02 0.80 2.0 1.60 1.10 3.2775 3.1979 2.43
03 0.80 2.3 1.84 1.13 3.1991 3.1240 2.35
04 0.80 3.0 2.40 1.20 2.9768 2.9360 1.37
05 1.20 1.0 1.20 1.50 3.1941 3.2541 −1.88
06 1.20 2.0 2.40 1.60 3.2775 3.1746 3.14
07 1.20 2.3 2.76 1.63 3.1991 3.1008 3.07
08 1.20 3.0 3.60 1.70 2.9768 2.9129 2.15
09 1.60 1.0 1.60 2.00 3.1941 3.2404 −1.45
10 1.60 2.0 3.20 2.10 3.2775 3.1646 3.44
11 1.60 2.3 3.68 2.13 3.1991 3.0902 3.40
12 1.60 3.0 4.80 2.20 2.9768 2.8918 2.86
13 2.00 1.0 2.00 2.50 3.1941 3.2300 −1.12
14 2.00 2.0 4.00 2.60 3.2775 3.1576 3.66
15 2.00 2.3 4.60 2.63 3.1991 3.0817 3.67
16 2.00 3.0 6.00 2.70 2.9768 2.8852 3.08
17 2.40 1.0 2.40 3.00 3.1941 3.2185 −0.76
18 2.40 2.0 4.80 3.10 3.2775 3.1526 3.81
19 2.40 2.3 5.52 3.13 3.1991 3.0722 3.97
20 2.40 3.0 7.20 3.20 2.9768 2.8835 3.13
DownLoad: CSV

Table 2.   Frequency values with variation in N (with Wn = 2 μm, B = 2.3).

Sl. no. N fosc (GHz)
(computed)
fosc (GHz)
(simulated)
Deviation (%)
01 05 3.1991 3.0817 3.67
02 07 2.2851 2.1993 3.76
03 09 1.7773 1.7123 3.66
04 11 1.4541 1.4008 3.67
05 13 1.2304 1.1861 3.60
06 15 1.0664 1.0274 3.65
07 17 0.9409 0.9071 3.59
08 19 0.8419 0.8114 3.62
09 21 0.7617 0.7341 3.62
10 23 0.6955 0.6705 3.60
DownLoad: CSV
[1]
Chebli R, Zhao X, Sawan M. A wide tuning range voltage-controlled ring oscillator dedicated to ultrasound transmitter. IEEE 16th International Conference on Microelectronics, 2004: 313 doi: 10.1109/ICM.2004.1434276
[2]
Eken Y A, Uyemura J P. A 5.9-GHz voltage-controlled ring oscillator in 0.18-μm CMOS. J Solid-State Circuits, 2004, 39: 230 doi: 10.1109/JSSC.2003.820869
[3]
Kang S M, Leblebici Y. CMOS digital integrated circuits: analysis and design. 3rd ed. McGraw-Hill Higher Education, 2002: 239
[4]
Retdian N, Takagi S, Fujii N. Voltage controlled ring oscillator with wide tuning range and fast voltage swing. IEEE Asia-Pacific Conference on ASIC, Tokyo, Japan, 2002
[5]
Jovanovic G, Stojcev M, Stamenkovic Z. A CMOS voltage controlled ring oscillator with improved frequency stability. Sci Pub State Univ Novi Pazar A, 2010, 2: 1
[6]
Rabaey J M, Chandrakasan A, Nikolic B. Digital integrated circuits – a design perspective. 2nd ed. Pearson Eduction, 2003: 194
[7]
Baker R J. CMOS: circuit design, layout, and simulation. 3rd ed. Wiley-IEEE Press, 2010: 337
[8]
Rout P K, Acharya D P. Design of CMOS ring oscillator using CMODE. IEEE International Conference on Energy, Automation, and Signal, 2011: 1
[9]
Mishra A, Sharma G K, Boolchandani D. Performance analysis of power optimal PLL design using five-stage CS-VCO in 180 nm. IEEE International Conference on Signal Propagation and Computer Technology, 2014: 764
[10]
Paydavosi N, Morshed T H, Lu D D, et al. BSIM4v4.8.0 MOSFET model - user’s manual. University of California, Berkeley, 2013
[11]
Yeo K S, Rofail S S, Goh W L. CMOS/BiCMOS ULSI. Pearson Education, 2002: 207
[12]
Farahabadi P M, Miar-Naimi H, Ebrahimzadeh A. Closed-form analytical equations for amplitude and frequency of high-frequency CMOS ring oscillators. IEEE Trans Circuits Syst I, 2009, 56: 2669 doi: 10.1109/TCSI.2009.2016179
[13]
Razavi B. Design of analog CMOS integrated circuits. 2nd Ed. McGraw Hill Education, 2001: 30
[14]
Weste N, Harris D. CMOS VLSI design: a circuits and systems perspective. 4th ed. Pearson Education, 2011
[15]
Uyemura J P. CMOS logic circuit design. Kluwer Academic Publishers, 2002: 21
[16]
Bhushan M, Ketchen M B. CMOS test and evaluation: a physical perspective. Springer, 2014: 381
[17]
Cheng Y, Hu C. MOSFET modeling and BSIM3 user’s guide. Kluwer Academic Publishers, 2002
[18]
Koithyar A, Ramesh T K. Analysis of deadbeat control for an integer-N charge-pump PLL. Proc Comput Sci, 21015, 70C, 2015, 70: 392
[19]
Koithyar A, Ramesh T K. Characterization of submicron ring oscillator using the first order design equations. IEEE International Conference on Communication and Signal Processing, 2016: 1227
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    Received: 21 September 2017 Revised: 27 November 2017 Online: Accepted Manuscript: 07 February 2018Uncorrected proof: 03 April 2018Published: 01 May 2018

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      Aravinda Koithyar, T. K. Ramesh. Frequency equation for the submicron CMOS ring oscillator using the first order characterization[J]. Journal of Semiconductors, 2018, 39(5): 055001. doi: 10.1088/1674-4926/39/5/055001 A Koithyar, T. K. Ramesh. Frequency equation for the submicron CMOS ring oscillator using the first order characterization[J]. J. Semicond., 2018, 39(5): 055001. doi: 10.1088/1674-4926/39/5/055001.Export: BibTex EndNote
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      Aravinda Koithyar, T. K. Ramesh. Frequency equation for the submicron CMOS ring oscillator using the first order characterization[J]. Journal of Semiconductors, 2018, 39(5): 055001. doi: 10.1088/1674-4926/39/5/055001

      A Koithyar, T. K. Ramesh. Frequency equation for the submicron CMOS ring oscillator using the first order characterization[J]. J. Semicond., 2018, 39(5): 055001. doi: 10.1088/1674-4926/39/5/055001.
      Export: BibTex EndNote

      Frequency equation for the submicron CMOS ring oscillator using the first order characterization

      doi: 10.1088/1674-4926/39/5/055001
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