1. Introduction

Motivated by achieving high breakdown voltage and high energy conversion efficiency simultaneously, ultra-wide bandgap semiconductor materials and devices with high carrier mobility are powerful competitors of the next generation power electronics. Ultra-wide bandgap materials like diamond, β-Ga₂O₃ and AlN have attracted most of the attentions, due to their high Baliga’s figure of merit (BFOM), defined as εμE_c³, where ε, μ and E_c are the dielectric constant, carrier mobility and critical breakdown field (E_c), respectively^[1–9]. Compared to diamond and AlN, the monoclinic β-Ga₂O₃ has the advantages of potential low cost and large size substrate through melt-grown method and the easy control of the n-type doping, while on the contrary, both diamond and AlN are difficult to be doped and the high quality single crystalline native substrate are extremely expensive^{[7, 8]}. β-Ga₂O₃ with an ultra-wide bandgap of 4.6–4.9 eV, estimated E_c = 8 MV/cm and decent intrinsic electron mobility limit of 250 cm²/(V·s), yielding a high BFOM of more than 3000, which is several times higher than that of GaN and SiC, showing that β-Ga₂O₃ is more promising candidate for power electronics by simultaneous achieving higher breakdown voltage (BV) and lower specific on-resistance (R_{on, sp}) from the material point of view.

Although some progresses have been achieved, the performance and development of β-Ga₂O₃ based devices are still far behind the GaN and SiC’s. While in fact, the research of β-Ga₂O₃ both on material and device still present itself as a virgin area, such that more universities, research institutes, national laboratories, and government funding are needed to have a fully discovering and understanding about the material properties, how to enhance device performances and make them comparable or even higher when compared with the device performance of GaN and SiC. In this review article, recent advances of the state-of-art material growth and device technologies are summarized, showing the great promise of β-Ga₂O₃ as power device channel material.

2. Basic material properties of β-Ga₂O₃

There are 5 polymorphs of β-Ga₂O₃, namely α, β, γ, δ, and ε^[10–15]. Among which, the monoclinic (β-) phase of β-Ga₂O₃ denotes the most stable one until its melting point, while other polymorphs are metastable and will convert into β phase at an elevated temperature (T) above 750–900 °C. The crystal structure and lattice parameters of β-Ga₂O₃ are shown in Fig. 1, with lattice constant a = 12.2 Å, b = 3.0 Å and c = 5.8 Å, respectively. The unit cell possesses two crystallographically inequivalent Ga positions, one with tetrahedral geometry Ga (I) and one with octahedral geometry Ga (II). The oxygen ions are arranged in ‘distorted cubic’ array. Oxygen atoms have three crystallographically different positions and are denoted as O(I), O(II) and O(III), respectively. Two oxygen atoms are coordinated trigonally and one is coordinated tetrahedrally. The different position of Ga and O atoms leads to an anisotropic optical, electrical and physical properties, for example its different thermal conductivity at (-201), (100), (010) and (100) planes. The upper valence and lower conduction band structure of β-Ga₂O₃, calculated from density functional theory (DTF) is shown in Fig. 2, as reported by He et al.^[13]. It is generally accepted that the bandgap from DFT is underestimated due to the ground state theory. More accurate bandgap value of β-Ga₂O₃ is extracted to be around 4.8 eV from hybrid DFT, which is in agreement with absorption and resolved photoemission experiment^{[16, 17]}. The electron effective mass is calculated to be around 0.3m_o, where m_o is the free electron mass. However, the flatness of valence band shows the large effective mass of holes, indicating an extremely low hole mobility even the p-type doping can be resolved. In addition to the challenges of the p-type doping and low hole mobility issues, the extremely low thermal conductivity of 10–25 W/(m·K) both from theoretical calculation and experiment turns out to be the most detrimental property of using β-Ga₂O₃ native substrate and potential solutions will be described in the future section.

3. Bulk substrate growth and thin film epitaxial growth

The success achieving of large diameter single crystalline and low defect density β-Ga₂O₃ native substrates is the main stimulation of devoting tremendous efforts to realize the application of β-Ga₂O₃ based materials and devices. Particularly, the development of melt-grown method offers the great promise of accomplishing low cost commercial substrates, which is advantageous over the growth techniques of SiC and bulk GaN. Standard growth techniques of β-Ga₂O₃ including Czochralski method (CZ)^[18–20], edge-defined film fed (EFG)^[21], floating-zone (FZ)^[22–24] and vertical Bridgman (VB)^[25–27] growth methods. Tomm et al. first studied the CZ growth of the β-Ga₂O₃ single crystals and later Galazka et al carried out a comprehensive study on the same method^{[28, 29]}. It is reported that a diameter of 2 inches cylindrical β-Ga₂O₃ single crystal have been demonstrated with this CZ method. It is generally accepted that the EFG is the most promising growth method for β-Ga₂O₃, combing the capability of achieving large size and high quality for future high-volume production, which is also a standard method for sapphire substrate. Growth rate as high as 15 mm/h and large size of 4 inches have been accomplished even at this premature stage, as shown in Fig. 3^[30]. FZ method is always used as a route to synthesis β-Ga₂O₃ rod for basic research purpose with typical growth rate of 6 mm/h and diameter of 10 mm. VB methods provide another useful alternative methodology to achieve β-Ga₂O₃ single crystals by providing the advantage of easy release of the crystals after growth. The single crystal with diameter of 25 mm is obtained through this method, as shown in Fig. 4^[31]. It should be noted that the unintentional incorporation of the Si and Ir atoms from the β-Ga₂O₃ seed and crucible leads to the unintentionally doped (UID) n-type conducting in the material so that deep acceptors like Mg and Fe are commonly used to compensate those n-type dopants to achieve the semi-insulating property.

Developing high quality β-Ga₂O₃ thin film epitaxial growth is of equal importance when compared to the β-Ga₂O₃ substrate, since β-Ga₂O₃ thin film always serve as the channel layer for power devices such as diodes and MOSFETs. Accurate control of the dopants and minimization of defects and imperfections are always two challenges for thin film epitaxial growth. Homoepitaxial growth of high quality β-Ga₂O₃ thin films on its native substrates can be carried out by the following major ways: metalorganic chemical vapor deposition (MOCVD)^[32–34], molecular beam epitaxy (MBE)^[35–38], halide vapor phase epitaxy (HVPE)^[39–42], mist-CVD and some other CVD techniques^[43–49]. MOCVD and MBE are two of the most popular epitaxial growth tools, which are widely used in GaAs and GaN epitaxial growth. Baldini et al. reported on growing Sn-doped homoepitaxial layer on (100) substrate with MOCVD^[50]. TEGA, molecular oxygen (O₂) and TESn were used as Ga, O and Sn precursors, respectively. The epi-layer has a RMS surface roughness of 0.6 nm and the main defects in the layers were stacking faults and twin lamella. Gogova et al. reported on achieving single-phase, smooth β-Ga₂O₃ layers doped with Si, with a dislocation density not exceeding those of the melt grown substrate. HRTEM image of grown thin film is shown in Fig. 5(a)^[33]. Okumura et al. reported on using plasma-assisted MBE to grow the (010) β-Ga₂O₃ under Ga-rich conditions at growth temperatures above 650 °C with growth rate about 2.2 nm/min. Slightly Ga-rich conditions between 650 and 750 °C are optimal for a smooth surface with an RMS surface roughness of 0.1 nm at a high growth rate. Surface roughness at various growth temperature is shown in Fig. 5(b)^[37]. HVPE is one of the most cost effective methodologies in terms of deposition rate, epi-layer quality and inexpensive facility. However, it generally ends up with a rough surface, which requires a post chemical mechanical polishing process to smooth. Murakami et al. reported on using GaCl and O₂ precursors for the HVPE of β-Ga₂O₃ thin film on (001) β-Ga₂O₃ substrate with a relative smooth surface morphology and low net carrier doping concentration of 10¹³ cm⁻³ at a limited growth rate of 5 μm/h and temperature of 1000 °C. The microscopy images of β-Ga₂O₃ surfaces after HVPE growth on (001) β-Ga₂O₃ substrates for 1 h at (c) 800 and (d) 1000 °C^[41] are shown in Fig. 5. Mist CVD is another inexpensive approach to grow different polymorphs of Ga₂O₃, like α-, β-, γ-phases at a relatively low growth temperature of 500–630 °C, while the solution is atomized via ultrasonication at a frequency of 2.4 MHz. Other phases can be transformed into β-phase after a high temperature annealing.

4. Device performances: diodes and FETs

As always emphasized by the β-Ga₂O₃ community, β-Ga₂O₃ holds promise for future power electronics due to its ultra-wide bandgap, high breakdown field and decent electron mobility induced high BFOM. Table 1 lists the comparisons of some major semiconductors as the channel materials for power devices. Some key FOMs used for representing how ideal of this material can be utilized for power electronics, such as Baliga, Johnson and Keys are also included. Baliga, Baliga high frequency, Johnson and Keyes FOMs are used to evaluate the power devices in terms of power handling capability and conduction loss, the measure of switching losses, the measure of suitability of a semiconductor material for high frequency power transistor applications and requirements, and the thermal dissipation capability for power density and speed, respectively. As shown in this Table 1, all other FOMs of β-Ga₂O₃ are significantly higher than that of SiC and GaN except Keyes FOM due to its obvious shortage of extremely-low thermal conductivity. Nevertheless, we should put all our endeavors to explore and demonstrate all its potentials and then push the device performance to its limit. Diodes and FETs are the most basic but most important elements of power electronics, which deserve thorough investigation. In this section, the most recent progresses of both diodes and FETs are comprehensively reviewed and solution to its low thermal conductivity issue is proposed.

4.1 Schottky barrier diodes on native substrates

Schottky Barrier Diodes (SBDs) with low turn on voltage (V_on), high forward current density and fast switching speed properties are ideal candidate for low switching/conduction losses and high frequency operations, which are indispensible components in power electronic circuits such as converters and inverters for power supplies and power factor corrections^[51]. Sasaki et al. developed the first β-Ga₂O₃ SBD on its (010) native substrate with a 1.4 μm thick ozone MBE homoepitaxial grown drift layer and a breakdown voltage (BV) of more than 100 V is achieved^[52]. The electron mobility of this Sn-doped thin film is reported to be as high as 100–150 cm²/(V·s) at a doping concentration range of 10¹⁶–10¹⁷ cm⁻³. The mobility versus doping concentration and I–V characteristics are included in Fig. 6.

Following the 1st β-Ga₂O₃ SBD, many research groups have demonstrated high performance SBDs with BV around or exceeding 1 kV with or without field-plate or edge termination techniques. Konishi et al. reported on the 1st achieving of the BV more than 1 kV with a field-plate structure and a 7-μm thick HVPE grown β-Ga₂O₃ drift layer^[53]. Diodes were fabricated by depositing full area back Ohmic contacts of Ti/Au (20 nm/230 nm) by E-beam evaporation, while the Schottky contacts were patterned by lift-off of E-beam deposited Schottky contacts Pt/Ti/Au (15 nm/5 nm/500 nm) on the epitaxial layers with a field plate length of 20 μm. The net donor concentration of this epitaxial layer is calculated to be 1.6 × 10¹⁶ cm⁻³ from C–V measurement. To achieve a high BV, a low density channel or drift layer is needed so as to flatten the electric field from the anode to cathode based on the Poisson Equation. The device has a specific on-resistance of 5.1 mΩ·cm², yielding a power FOM of 227 MW/cm², combined with the BV of 1076 V. The peak E at anode edge is simulated to be 5.1 MV/cm, which is much higher than the E_C of GaN and SiC. Fig. 7 shows the details of the device schematic, forward and reverse J–V characteristics.

Yang et al. also demonstrated 1 kV-class vertical β-Ga₂O₃ SBD without field-plate structure with a 10-μm thick β-Ga₂O₃ drift layer and Ni/Au as the anode^[54]. The native substrate possesses a pit dislocation of 10³ cm⁻² and the epitaxial layer has a net doping concentration of 2 × 10¹⁶ cm⁻³. It is found that the BV has a strong dependence on the anode diameter and the BV is around 1 KV and 800 V at an anode diameter of 105 and 205 μm, respectively, as shown in Fig. 8(a). The diode is also reported to achieve a high power FOM of 150 MW/cm² with a R_on,sp of 6 mΩ·cm². By further shrinking the anode diameter to 25 μm, the BV is further increased to be 1.6 kV at a decent power FOM of 100 MW/cm², as shown in Fig. 8(b)^[55]. This anode diameter dependent BV is most likely related with defects in the epitaxial layer. With larger anode area, higher quantities of defects are expected underneath the anode so that once a point defect is damaged under the high E condition the whole diode is destroyed, resulting in a reduced BV. Through growth optimization, the carrier concentration in the epitaxial layer can be further reduced to 2 × 10¹⁵ cm⁻³. Combined with a 20-μm thick drift layer, the BV can be enhanced to 2300 V. Meanwhile, a high current of 2 A can be also achieved by enlarging the anode area to 0.2 cm^2[56].

4.2 Field effect transistors (FETs) on native substrates

4.2.1   Depletion-mode high-power FETs

The first metal-semiconductor-FET (MESFET) was demonstrated by Higashiwaki et al. with a Sn-doped β-Ga₂O₃ epitaxial channel on a semi-insulating (010) β-Ga₂O₃ substrate^[57]. This circular MESFET is with a gate length (L_G) of 4 μm and source-drain (L_SD) of 20 μm demonstrates a BV of more than 250 V, drain current (I_D) of 15 mA and on/off ratio around 10⁴. Output and transfer characteristics are plotted in Fig. 9. Following the MESFET, metal-oxide-semiconductor FETs (MOSFETs) start to attract the power device community’s attention to resolve the shortcomings of the MESFET. The first lateral depletion-mode (D-mode) β-Ga₂O₃ MOSFET power device with BV more than 600 V was reported by Wong et al.^[58]. The device structure is shown as Fig. 10(a) with a MBE grown and Si-doped channel with doping concentration of 3 × 10¹⁷ cm⁻³, a heavily doped source and drain contacts and a FP length of 2.5 μm. A maximum I_D of 80 mA/mm, peak g_m of 3.5 mS/mm and high on/off ratio of more than 10⁹ are achieved simultaneously. Pulsed I_D–V_DS shows no current collapse phenomenon, verifying the great promise of β-Ga₂O₃ MOSFET as a candidate for power device application. Recently, Zeng et al. has pushed the BV to be 1850 V by adopting a FP structure and a 400-nm thick composite field plate oxide at a L_GD = 20 μm^[59]. It is believed that the introduction of another 50 nm of ALD SiO₂ is helpful in improving the BV, rather than a simply plasma-enhanced CVD (PECVD) SiO₂ layer underneath the gate FP electrode, where the premature breakdown happens and also a high-quality ALD SiO₂ is available to sustain a higher E_C. The device structure and breakdown characteristics are described in Fig. 11.

4.2.2   Enhancement-mode (E-mode) high-power FETs

Zeng et al. reported on achieving the first E-mode β-Ga₂O₃ MOSFET by adopting a high work function Au gate electrode and low doping (6 × 10¹⁵ cm⁻³) MBE β-Ga₂O₃ channel, so that E-mode operation with V_T of 3 V and BV of 400 V are demonstrated^[60]. Later, Tadjer et al. fabricated a (001) β-Ga₂O₃ MOSFET with V_T = 2.9 V and HfO₂ as the gate dielectric^[5]. Figs. 12(a) and 12(b) are the I_D–V_GS characteristics of Zeng’s and Tadjer’s E-mode MOSFET. Chabak et al. demonstrated the E-mode β-Ga₂O₃ MOSFET via incorporating a fin-array structure with triangular fin-width of 300 nm and fin-height of 200 nm, such that the high work function Ni gate electrode can deplete the β-Ga₂O₃ channel from two side walls with V_T around 1 V^[4]. On/OFF ratio greater than 10⁵ and a three-terminal BV of more than 600 V are achieved at a 21-μm gate-drain spacing, as shown in Fig. 13. Hu et al. has adopted a similar Fin-structure to achieve an E-mode operation on a vertical MOSFET^[61]. A 10-μm thick HVPE β-Ga₂O₃ layer on (001) substrate with low charge doping concentration of 2 × 10¹⁶ cm⁻³ is used as the starting wafer. By shrinking the fin-width to 330 nm or even smaller, the V_T is extracted to be 1.2–2.2 V. A current on/off ratio of 10⁸, R_on,sp of 13–18 mΩ·cm², BV up to 1057 V and output current of more than 200 A/cm² are demonstrated. Figs. 14(a)–14(d) depict the device structure of the vertical E-mode β-Ga₂O₃ MOSFET, on-state I_D–V_GS and three-terminal OFF-state breakdown measurement results, respectively.

4.2.3   High frequency RF Power FETs

Green et al. reported on demonstrating the first β-Ga₂O₃ RF transistor on a Si-doped MOCVD β-Ga₂O₃ channel with doping concentration of 10¹⁸ cm⁻³ and a (100) substrate^[62]. By recessing the β-Ga₂O₃ epi-channel, peak transconductance of 21 mS/mm and extrinsic cut-off frequency (f_T) and maximum oscillation frequency (f_max) of 3.3 GHz and 12.9 GHz are achieved. Meanwhile, CW class-A power amplifier demonstrate a output power density (P_out), power gain, and power-added efficiency (PAE) of 0.23 W/mm, 5.1 dB and 6.3%, respectively at the frequency of 800 MHz. Device structure, small signal and large signal performances are described in Fig. 15. Singh et al. carried out the study on the pulsed large signal RF performance of field-plated β-Ga₂O₃ MOSFET^[63]. It is revealed that reduced self-heating when pulse resulted in a PAE of 12%, drain efficiency of 22.4%, P_out of 0.13 W/mm and a maximum gain up to 4.8 dB at 1 GHz for a device with L_g = 2 μm. Self-heating effect at high V_DS and I_DS caused by the low thermal conductivity is the main factor limiting the device performances, while the trapping effect has the minimal impact on the performance degradation. Pulsed I_D–V_DS measurement and large signal load pull measurement results are shown in Fig. 16 and the comparison between CW and pulsed results are shown in Table 2, indicating the self-heating effect is the primary detrimental factor of degrading device performance. Chabak et al. reported on achieving high performance β-Ga₂O₃ RF transistor by utilizing a higher doped but thinner Si doped MOVPE (100) channel with sub-micron T-shape gate^[64]. A record-high f_T/f_max of 5/17 GHz at V_DS = 15 V and V_GS = −14.2 V is achieved, along with a peak g_m of 25 mS/mm. DC and RF results are shown in Fig. 17.

4.3 High performance nano-membrane β-Ga₂O₃ SBDs and FETs on foreign substrates

4.3.1   Field-plated lateral β-Ga₂O₃ SBDs on sapphire substrate

β-Ga₂O₃ crystal possesses an unique property that its (100) surface has a large lattice constant of 12.23 Å along [100] direction, which allows a facile cleavage into thin belts or nano-membranes^[65]. Hence, by transferring β-Ga₂O₃ nano-membrane from its bulk substrate to a wider bandgap and higher thermal conductivity substrate can minimize low-thermal conductivity of β-Ga₂O₃ bulk substrate induced severe self-heating effect while maintaining its high breakdown characteristics. Importantly as a research route, it provides an effective methodology to investigate fundamental material property of β-Ga₂O₃ and fully explore device potentials without using many β-Ga₂O₃ epitaxy wafers. Hu et al. reported on the first high performance lateral β-Ga₂O₃ SBD on sapphire substrate by transferring high quality β-Ga₂O₃ nano-membrane channel from its low defect density bulk substrate^[66]. Annealed Ti/Au (60/120 nm) is used as the cathode while Ni/Au (60/120 nm) is used as the anode metal and the β-Ga₂O₃ nano-membrane is with thickness around 400 nm. The SBDs have an on-current on/off ratio of 10⁷–10⁸ with turn-on voltage (V_on) of 1 V determined by the linear extrapolation of the forward I–V. The R_{on, sp} of each SBD is determined to be R_on = 3.29, 5.94, 12.7, and 34.2 mΩ·cm² for L_{Schottky-Ohmic} = 4, 6, 11, and 15 μm, respectively. The off-state BV is measured to be 0.64 kV, 0.85 kV, 1.2 kV and 1.7 kV, yielding a power FOM of 0.124, 0.121, 0.113, and 0.09 GW/cm² for L_{Schottky-Ohmic} = 4, 6, 11, and 15 μm, respectively, by considering the FOM = BV²/R_{on, sp}. Device structure, forward I–V and reverse breakdown characteristics are shown in Fig. 18. Following the first lateral β-Ga₂O₃ SBD, Hu et al. also developed a field-plated lateral β-Ga₂O₃ SBD with record-high reverse blocking voltage of more than 3 kV and high DC power FOM of 500 MW/cm^2[51]. In this study, an even thicker (650 nm) β-Ga₂O₃ nano-membrane channel is used to improve the on-current and hence reducing the R_on,sp and the field plate structure is used to mitigate the E crowding effect at the anode edge. The record-high BV of more than 3 kV is demonstrated on a SBD with L_{Schottky-Ohmic} = 24 μm with low R_on,sp of 24.3 mΩ·cm². In addition to the high BV of more than 3 kV, a record high power FOM of 0.5 GW/cm² is also achieved on the SBD with L_{Schottky-Ohmic} = 16 μm and BV = 2.25 kV. The device structure, reverse characteristics and benchmark comparisons between lateral and vertical SBDs are shown in Fig. 19.

4.3.2   High performance back-gate D/E-modes β-Ga₂O₃ on insulator (GOOI) FETs

Zhou et al. reported on achieving record-high on-current with a back-gated FETs based on β-Ga₂O₃ nano-membrane channels^{[67, 68]}. Figs. 20(a) and 20(b) are the schematic of a GOOI FET and atomic force microscopy (AFM) image of a β-Ga₂O₃ surface after cleavage, which shows atomically flat and uniform within the whole nano-membrane. Device fabrication commenced with 6 mm by 6 mm (-201) β-Ga₂O₃ bulk substrate with Sn doping concentration of 3 × 10¹⁸ cm⁻³ and 8 × 10¹⁸ cm⁻³. Various β-Ga₂O₃ nano-membranes with thickness from 50 to 150 nm, confirmed by the AFM measurements, were chosen for the device fabrication. Fig. 21(a) presents the D-mode DC output characteristics (I_D–V_DS). Devices have a L_CH of 0.3 μm, channel width (W) of 0.15 μm and channel thickness (t) of 70 nm for 8.0 × 10¹⁸ cm⁻³, and W = 0.6 μm and t = 100 nm for 3.0 × 10¹⁸ cm⁻³ device, respectively. A record high maximum I_D (I_DMAX) of 1.5 A/mm is obtained, which is more than 2 times of lower doping channel. The device also has a much lower R_on of 5 Ω·mm compared with that of 11 Ω·mm with 3.0 × 10¹⁸ cm⁻³ doping concentration. Fig. 21(b) is the log-scale I_D–g_m–V_GS transfer characteristics of the same D-mode GOOI FET with 8.0 × 10¹⁸ cm⁻³ doping concentration. This D-mode GOOI FET has a threshold voltage (V_T) of −135 V, extracted from the log-scale I_D–V_GS at V_DS = 1 V and I_D = 0.1 mA/mm. Figs. 21(c) and 21(d) depict the I_D–V_DS output and I_D–g_m–V_GS transfer characteristics of an E-mode GOOI FET with L_CH = 0.3 μm, t = 55 nm and W = 0.17 μm for 8.0 × 10¹⁸ cm⁻³, and t = 75 nm and W = 0.45 μm for 3.0 × 10¹⁸ cm⁻³ device also shown in Fig. 21(c) as black dashed curves for comparison. A record high I_DMAX = 1.0 A/mm for higher doping channel is obtained, which is more than 80% higher than lower doping channel. E-mode GOOI FET has a V_T of 2 V determined from the I_D–V_GS at V_DS = 1 V and I_D = 0.1 mA/mm. Further scaling the L_CH shows no significant help in boosting the I_DMAX, which is primarily limited by the high R_C of low doping channel underneath the contact. The improved I_DMAX of D/E-mode devices mainly originate from the higher doping concentration induced lower R_c rather than the simply L_CH scaling. Finally, benefiting from its wide-bandgap and a low damage transfer process, both D/E-mode devices have achieved high on/off ratio of 10¹⁰ and low SS of 150–165 mV/dec for a 300 nm thick SiO₂.

4.3.3   VT dependence on the β-Ga₂O₃ Nano-membrane Thickness

It is found that the V_T shifts from negative values in D-mode to positive values in E-mode by shrinking β-Ga₂O₃ nano-membrane thickness. Fig. 22(a) describes the thickness dependent representative I_D–V_GS characteristics. Obviously, the V_T is shifted from negative to positive when the thickness is slowly reduced. Fig. 22(b) summarizes the extracted thickness dependent V_T of 15 devices. Generally, they all follow the same trend as shown in Fig. 22(a). The determined thickness dependent V_T may be valuable in the realization of high performance top gate E-mode GOOI FETs in the near future.

The significant V_T shift with respect to different β-Ga₂O₃ nano-membrane thickness is due to the surface depletion of the unpassivated device surface, which has tremendous dangling bonds and surface states on the device surface^[69]. This is the reason why E-mode GOOI FETs can also be realized in high doping β-Ga₂O₃ nano-membrane. The surface depletion effect could be verified by using ALD to deposit 15 nm Al₂O₃ on top to passivate the top surface. As shown in Fig. 23(a), the V_T is significantly shifted to the left for more than 70 V after an ALD passivation, verifying the existence of top and bottom surface depletion on unpassivated GOOI FET surfaces. Based on the surface depletion, each surface depleted charge density (n_s) can be estimated by using the TCAD C–V simulation to match the measured and simulated V_T from E-mode devices with V_T near zero. The n_s is determined and simulated to be 1.2 × 10¹³ cm⁻² and 2.2 × 10¹³ cm⁻² for 3.0 × 10¹⁸ cm⁻³ and 8.0 × 10¹³ cm⁻³ nano-membranes with thickness of 80 nm and 55 nm, respectively. Higher n_s for higher doping β-Ga₂O₃ nano-membrane is most likely related to the higher surface states with more Sn⁺⁴ dopants. Therefore, the actual C–V curve and I_D–V_GS curves are significantly shifted to the right compared with the ideal case without considering surface depletion. Fig. 23(b) shows the simulated C–V curve for E-mode GOOI FET and the V_T from C–V simulation is in good agreement with the V_T from I_D–V_GS characterization. Figs. 23(c) and 23(d) are the simulated band diagram of the E-mode GOOI FET at V_GS = 0 V with lower doping and higher doping channels by considering surface depletion effect. The top and bottom depletion regions pull up the conduction band of β-Ga₂O₃ with very few carriers left behind in the nano-membrane, so that E-mode GOOI FET can be formed.

4.3.4   Solutions to the severe self-heating effects on β-Ga₂O₃ FETs

Self-heating effect induced temperature increase and non-uniform distribution of dissipated power have emerged as one of the most dominant concerns in the degradation of the I_D, output power density (P), as well as the gate leakage current, device variability, and reliability^[70]. This effect would become severe in high power device with a low thermal conductivity (κ) substrate such as β-Ga₂O₃, whose κ is just 10–25 W/m·K, which has become one of major challenges to realize practical application. An effective approach to mitigate low κ problem is to utilize a higher κ substrate rather than the β-Ga₂O₃ native substrate through a potential wafer bonding technique. Nowadays, all the GOOI FETs were fabricated on the SiO₂/Si substrate, however the κ of SiO₂ is just 1.5 W/(m·K). For the thermal management of GOOI FETs, a higher κ substrate is urgently needed. Diamond has the highest thermal conductivity (κ = 1000–2200 W/(m·K)) among all available substrates; thus, it is of great interest to investigate the heat dissipation effect of β-Ga₂O₃ devices on diamond. Meanwhile, diamond is also a current blocking substrate for transferred β-Ga₂O₃ nano-membranes due to its wide bandgap of 5.47 eV. In this section, sapphire and diamond substrates are used as a thermal conductor for GOOI FETs to solve the severe self-heating effect and enhance the thermal dissipation and boost device performance^{[71, 72]}. An ultra-fast, high-resolution thermos-reflectance (TR) imaging technique^[73] is introduced and then applied to the top-gate GOOI FET to examine the reduced self-heating effect and local surface temperature increase magnitude on sapphire and diamond substrates compared with SiO₂/Si substrate. After substituting SiO₂/Si with sapphire and diamond substrates, the top-gate GOOI FET has 70% and 2 times higher I_DMAX, ~ 3 times and 8 times lower device surface temperature change ΔT, and 3 times and 8 times lower thermal resistance (R_T), respectively.

Figs. 24 (a)–24(c) are the device schematic and SEM images of fabricated GOOI FETs, respectively. Source and drain regions were defined by the VB6 EBL, followed by Ti/Al/Au (15/60/50 nm) metallization and lift-off processes. 15 nm of Al₂O₃ was deposited by ASM F-120 ALD at 180 °C with tri-methyl-aluminum (TMA) and H₂O as precursors. Finally, Ni/Au (50/50 nm) is deposited as the gate electrode, followed with lift-off process.

Figs. 25(a), 25(b) and 25(c) show the well-behaved DC I_D–V_DS of three top-gate GOOI FETs with L_SD of 6/6.5 μm, L_G of 1 μm, and channel thickness of 73/75/74 nm on SiO₂/Si, sapphire and diamond substrates, respectively. I_DMAX of 960, 535 and 325 mA/mm for diamond, sapphire and SiO₂/Si substrates are obtained. I_DMAX of GOOI FET on diamond and sapphire substrates is around 3 times and 1.7 times of that on SiO₂/Si substrate, originating from better transport properties at a lower device temperature. Fig. 25(d) is the I_D–V_DS comparison at a fixed V_GS = 6 V. Figs. 25(e) and 25(f) depict the I_D–V_GS and g_m–V_GS of GOOI FETs on three substrates at V_DS = 25 V. High on/off ratio of 10⁹ and low SS of 65 mV/dec are achieved on both devices due to the wide bandgap and high-quality ALD Al₂O₃/β-Ga₂O₃ interface, yielding a low interface trap density (D_it) of 2.6 × 10¹¹ eV⁻¹·cm⁻² by the equation SS = 60 × (1 + qD_it/C_ox) mV/dec at room temperature, where C_ox is the oxide capacitance. One interesting phenomenon is that the peak g_m of diamond and sapphire substrate is 34 mS/mm and 21 mS/mm, which is around 2 times and 60% higher than the g_m of SiO₂/Si substrate. The extrinsic electron field-effect mobility (μ_FE) of GOOI FET on diamond, sapphire and SiO₂/Si are roughly extracted to be 43, 30.2 and 21.7 cm²/(V·s), respectively, benefiting from the less SHE on diamond.

Figs. 26(a), 26(b) and 26(c) are the merged optical and TR thermal image views of GOOI FETs on SiO₂/Si, sapphire and diamond substrates at steady state and different P conditions. As higher V_DS is applied, the device is heated up simultaneously and the corresponding ΔT is increased. At P = 717 W/mm² on the SiO₂/Si substrate, the ΔT is measured to be 106 K, whereas in contrast the ΔT is just 43 and 21 K at a higher P = 917 W/mm² and P = 1237 W/mm² on the sapphire and diamond substrates, respectively. Fig. 26(d) depicts the measured and simulated ΔT versus P (W/mm²) for the Ga₂O₃ FETs on a diamond substrate, performed both by TR imaging and Raman thermography. Good agreement among these three methods can be observed, with the highest temperature measured by Raman thermography to be 164 °C (ΔT = 141 K) at DC output power of 6565 W/mm² (64.7 W/mm or V_DS = 35 V for this particular exfoliated FET geometry). Fig. 26(e) shows the good agreement of the TR measured and the simulated ΔT versus P (W/mm²) on different substrates. For both the measurement and simulation results, the clear observation is that at the same P, the GOOI FET on the diamond substrate has more than 8 times lower ΔT compared to that on SiO₂/Si. The R_T of diamond, sapphire and SiO₂/Si substrates are calculated to be 1.71 × 10⁻², 4.62 × 10⁻² and 1.47 × 10⁻¹ mm²·K/W, respectively, through R_T = ΔT/P. The reduced R_T of GOOI FET on diamond and sapphire demonstrate that a higher κ substrate can be more effective in dissipating the heat on the devices. With less heat on the device, the temperature is lower so that the μ is higher to achieve a higher I_DMAX of 960 mA/mm for a better device performance.

4.3.5   β-Ga₂O₃ nano-membrane ferroelectric (FE)-FET with steep ss for wide bandgap logic application

High-temperature solid-state devices and circuits are required for many applications such as in aerospace, automotive, nuclear instrumentations and geothermal wells. Silicon-based complementary metal–oxide–semiconductor (CMOS) technology is not able to operate at such high temperatures, which is limited by its relatively small band gap of 1.12 eV. CMOS circuits using wide band gap semiconductors are promising in these high temperature logic applications. As for the logic application, steep SS is required so as to minimize the power supply so that power consumption and SHE are less severe. In this section, β-Ga₂O₃ FE-FETs with ferroelectric HZO as a gate dielectric stack is reviewed^[74]. Fig. 27(a) shows the schematic diagram of β-Ga₂O₃ FE-FETs, which consists of a 86 nm thick β-Ga₂O₃ nanomembrane as the channel, a 3 nm amorphous Al₂O₃ layer and a 20 nm polycrystalline HZO layer as the gate dielectric, a n⁺⁺ silicon substrate as the gate electrode, and a Ti/Au source/drain as the metal contacts. Fig. 27(b) shows the false-color SEM image of the fabricated β-Ga₂O₃ FE-FETs with four different channel lengths, capturing the β-Ga₂O₃ membrane and the Ti/Au electrodes.

Fig. 28(a) shows the normalized I_D–V_GS characteristics in the log scale of a β-Ga₂O₃ FE-FET. The back-gate bias is swept from −0.4 to 2 V in 40 mV per step, whereas the V_DS is biased at 0.1, 0.5, and 0.9 V. The whole sweep takes roughly 1 min. This device has a L_CH of 0.5 μm and a thickness of 86 nm. This particular thickness is chosen to tune the V_T slightly above zero. The I_D−V_GS characteristics were measured in bidirectional both forwardly (V_GS from low to high) and reversely (V_GS from high to low). SS is extracted as a function of I_D for both forward sweep (SS_min,For) and reverse sweep (SS_min,Rev) at various V_DS. Figs. 28(b)–28(d) show the SS–I_D characteristics extracted from Fig. 28(a) at V_DS = 0.1, 0.5, and 0.9 V, respectively. The device exhibits SS_min,For = 57.2 mV/dec and SS_min,Rev = 41.0 mV/dec at V_DS = 0.1 V, SS_min,For = 53.1 mV/dec and SS_min,Rev = 34.3 mV/dec at V_DS = 0.5 V, and SS_min,For = 55.0 mV/dec and SS_min,Rev = 34.4 mV/dec at V_DS = 0.9 V. SS less than 60 mV/dec at room temperature is demonstrated for both forward and reverse V_GS sweeps even at relatively high V_DS. Ga₂O₃ MOSFETs with 15 nm Al₂O₃ as a gate dielectric exhibit a minimum SS = 118.8 mV/dec. SS–I_D characteristics at different V_DS are similar, slightly better at high V_DS because of the larger impact of a Schottky barrier at lower V_DS. Because of the large band gap of β-Ga₂O₃, the band-to-band tunneling current at high V_DS is suppressed. Fig. 29(a) shows the I_D–V_GS characteristics in the linear scale of the same β-Ga₂O₃ FE-FET as in Fig. 28. V_T is extracted by linear extrapolation at V_DS = 0.1 V for both forward and reverse V_GS sweeps. V_T in the forward V_GS sweep (V_{T, For}) is extracted as 0.47 V, whereas V_T in the reverse V_GS sweep (V_{T, Rev}) is extracted as 0.38 V. Hence, the E-mode operation with V_T greater than zero for both forward and reverse V_GS sweeps is demonstrated. A negligible hysteresis is obtained for both on-state (high V_GS, as shown in Fig. 10(a)) and off-state (low V_GS, as shown in Fig. 28(a)), except that when V_GS is near the V_T region. At the V_T, low hysteresis is achieved to be 90 mV, calculated by using |V_{T, Rev} − V_{T, For}|, showing the great promise of using β-Ga₂O₃ for wide bandgap logic applications.

5. Conclusions

In conclusion, significant progresses have been achieved with remarkable power device performances even at this premature development stage, such as BV more than 3 kV of lateral Schottky Rectifiers, high current density 1.5/1 A/mm of D/E-modes FETs, BV of 1.8 kV for field-plated lateral MOSFET and f_T/f_amx of 5.1/17.1 GHz, respectively. In addition to device performance, sufficient low defect density less than 10³ cm⁻² of melt-grown native substrate and very smooth surface with RMS roughness less than 0.5 nm of epitaxial β-Ga₂O₃ thin film on its native substrate have all been demonstrated. However, some open questions about how to realize p-type β-Ga₂O₃ and how to resolve the low thermal conductivity issue are yet to be established. Once resolving those aforementioned issues, the bright future of β-Ga₂O₃ devices as power electronic products are definitely coming soon.