J. Semicond. > 2019, Volume 40 > Issue 9 > 091002
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REVIEWS

Reducing the power consumption of two-dimensional logic transistors

Weisheng Li†, Hongkai Ning†, Zhihao Yu, Yi Shi and Xinran Wang

+ Author Affiliations

 Corresponding author: Zhihao Yu, zhihao@nju.edu.cn; Xinran Wang, xrwang@nju.edu.cn

DOI: 10.1088/1674-4926/40/9/091002

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Abstract: The growing demand for high-performance logic transistors has driven the exponential rise in chip integration, while the transistors have been rapidly scaling down to sub-10 nm. The increasing leakage current and subthreshold slope (SS) induced by short channel effect (SCE) result in extra heat dissipation during device operation. The performance of electronic devices based on two-dimensional (2D) semiconductors such as the transition metal dichalcogenides (TMDC) can significantly reduce power consumption, benefiting from atomically thin thickness. Here, we discuss the progress of dielectric integration of 2D metal–oxide–semiconductor field effect transistors (MOSFETs) and 2D negative capacitance field effect transistors (NCFETs), outlining their potential in low-power applications as a technological option beyond scaled logic switches. Above all, we show our perspective at 2D low-power logic transistors, including the ultra-thin equivalent oxide thickness (EOT), reducing density of interface trap, reliability, operation speed etc. of 2D MOSFETs and NCFETs.

Key words: 2D materials, dielectric integration, interface, NCFETs, subthreshold slope, low power



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Fig. 1.  (Color online) Integrating ultra-thin high-κ dielectric on 2D materials. (a) The 3D AFM image of HfO2 deposited directly on MoS2 by ALD technique forms an island structure[26]. (b) Schematic of top gate FET based on monolayer 2D TMDC[7]. (c) Requirement of high-κ dielectric on 2D materials for low power device; (d) Device schematic of the top-gated MoS2 FET with HfO2 dielectric deposited by ozone pretreatment[31]. (e) Structural schematic of few layer MoS2 covered with the metal oxide buffer layer and HfO2 film[33]. (f) Illustration of the atomic structure of the bilayer MoS2 FETs with a CaF2 gate dielectric[35]. A quasi-van der Waals interface is formed between the F-terminated CaF2 (111) and the MoS2 channel. (g) PTCA coated graphene. PTCA selectively adheres to graphene on SiO2 surfaces, providing binding sites for ALD deposition. Inset is a top view of PTCA structure[38].

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Fig. 2.  (Color online) Basic concept of NC and ultra-low power NCFETs based on 2D TMDC. (a) Schematic of two capacitors in series. Vint is the voltage at the interface, equaling to the radio of gate voltage V and body factor m. (b) Gibb’s free energy-polarization (U–P) diagram[58] of FE, DE, and a series of them for capacitance matching and stabilization of negative capacitance. (c) Polarization–Voltage (P–V) curves deducted from U–P curves in (b). An S-shaped curve of FE is shown. (d) Polarization–electric field (P–E) loop of ferroelectric HZO and the schematic of back gate MoS2 NCFETs. (e) ID–VGS curves of a MoS2 NCFET[16] on 4 nm AL2O3/20 nm HZO (black: forward sweep, red: reverse sweep, grey: gate leakage) and control device with the same channel length of 1.7 μm on 25 nm Al2O3 (blue) at VDS = 0.1 V. (f) A brief summary of representative SS-hysteresis data of reported 2D NCFETs, including MoS2 FETs with HZO[16, 18, 54, 55], PVDF[59], CIPs[60, 61], and WSe2 FETs with HZO dielectric[56, 57], while three typical works based on Si are selected for comparation. According to ITRS 2.0[6], the requirements for scaled SS, 40 mV/dec in 2024, 25 mV/dec in 2030, are plotted respectively.

DownLoad: Full-Size Img PowerPoint
[1]
Lange K, Müller-Seitz G, Sydow J, et al. Financing innovations in uncertain networks—Filling in roadmap gaps in the semiconductor industry. Research Policy, 2013, 42, 647 doi: 10.1016/j.respol.2012.12.001
[2]
Waldrop M M. The chips are down for Moore’s law. Nat News, 2016, 530, 144 doi: 10.1038/530144a
[3]
Liu W, Kang J, Cao W, et al. High-performance few-layer-MoS2 field-effect-transistor with record low contact-resistance. IEEE International Electron Devices Meeting, 2013, 19
[4]
Martin C. Towards a new scale. Nat Nanotechnol, 2016, 11, 112 doi: 10.1038/nnano.2016.8
[5]
Kwon D, Chatterjee K, Tan A J, et al. Improved subthreshold swing and short channel effect in FDSOI n-channel negative capacitance field effect transistors. IEEE Electron Device Lett, 2017, 39, 300 doi: 10.1109/LED.2017.2787063
[6]
International Technology Roadmap for Semiconductors 2.0 (ITRS2. 0). Semiconductor Industry Association, 2015
[7]
Radisavljevic B, Radenovic A, Brivio J, et al. Single-layer MoS2 transistors. Nat Nanotechnol, 2011, 6, 147 doi: 10.1038/nnano.2010.279
[8]
Liu H, Neal A T, Ye P D. Channel length scaling of MoS2 MOSFETs. ACS Nano, 2012, 6, 8563 doi: 10.1021/nn303513c
[9]
Desai S B, Madhvapathy S R, Sachid A B, et al. MoS2 transistors with 1-nanometer gate lengths. Science, 2016, 354, 99 doi: 10.1126/science.aah4698
[10]
Alam K, Lake R K. Monolayer MoS2 transistors beyond the technology road map. IEEE Trans Electron Devices, 2012, 59, 3250 doi: 10.1109/TED.2012.2218283
[11]
Wang Q H, Kalantar-Zadeh K, Kis A, et al. Electronics and optoelectronics of two-dimensional transition metal dichalcogenides. Nat Nanotechnol, 2012, 7, 699 doi: 10.1038/nnano.2012.193
[12]
Yu Z, Ong Z Y, Li S, et al. Analyzing the carrier mobility in transition-metal dichalcogenide MoS2 field-effect transistors. Adv Fun Mater, 2017, 27, 1604093 doi: 10.1002/adfm.201604093
[13]
Fiori G, Bonaccorso F, Iannaccone G, et al. Electronics based on two-dimensional materials. Nat Nanotechnol, 2014, 9, 768 doi: 10.1038/nnano.2014.207
[14]
Chhowalla M, Jena D, Zhang H. Two-dimensional semiconductors for transistors. Nat Rev Mater, 2016, 1, 16052 doi: 10.1038/natrevmats.2016.52
[15]
Cheung K P. On the 60 mV/dec@ 300 K limit for MOSFET subthreshold swing. Proceedings of 2010 International Symposium on VLSI Technology, System and Application, 2010, 72
[16]
Yu Z, Wang H, Li W, et al. Negative capacitance 2D MoS2 transistors with sub-60 mV/dec subthreshold swing over 6 orders, 250 μA/μm current density, and nearly-hysteresis-free. IEEE International Electron Devices Meeting (IEDM), 2017, 23.6.1
[17]
Salahuddin S, Dattat S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett, 2008, 8, 405 doi: 10.1021/nl071804g
[18]
Si M, Su C J, Jiang C, et al. Steep-slope hysteresis-free negative capacitance MoS2 transistors. Nat Nanotechnol, 2018, 13, 24 doi: 10.1038/s41565-017-0010-1
[19]
Himpsel F J, McFeely F R, Taleb-Ibrahimi A, et al. Microscopic structure of the SiO2/Si interface. Phys Rev B, 1988, 38, 6084 doi: 10.1103/PhysRevB.38.6084
[20]
Robertson J. High dielectric constant oxides. Eur Phys J-Appl Phys, 2004, 28, 265 doi: 10.1051/epjap:2004206
[21]
Robertson J. High dielectric constant gate oxides for metal oxide Si transistors. Rep Prog Phys, 2005, 69, 327 doi: 10.1088/0034-4885/69/2/R02
[22]
Auth C, Cappellani A, Chun J S, et al. In 45 nm high k metal gate strain-enhanced transistors. Symposium on VLSI Technology, 2008, 128
[23]
George S M. Atomic layer deposition: an overview. Chem Rev, 2009, 110, 111 doi: 10.1021/cr900056b
[24]
Cowdery-Corvan P J, Levy D H, Nelson S F, et al. Process for atomic layer deposition. Google Patents, 2012
[25]
Krivokapic Z, Rana U, Galatage R, et al. 14 nm ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications. IEEE International Electron Devices Meeting (IEDM), 2017, 15.1.1
[26]
McDonnell S, Brennan B, Azcatl A, et al. HfO2 on MoS2 by atomic layer deposition: adsorption mechanisms and thickness scalability. ACS Nano, 2013, 7, 10354 doi: 10.1021/nn404775u
[27]
Yang J, Kim S, Choi W, et al. Improved growth behavior of atomic-layer-deposited high-k dielectrics on multilayer MoS2 by oxygen plasma pretreatment. ACS Appl Mater Interfaces, 2013, 5, 4739 doi: 10.1021/am303261c
[28]
Yang W, Sun Q Q, Geng Y, et al. The integration of sub-10 nm gate oxide on MoS2 with ultra low leakage and enhanced mobility. Sci Rep, 2015, 5, 11921 doi: 10.1038/srep11921
[29]
Azcatl A, Santosh K, Peng X, et al. HfO2 on UV–O3 exposed transition metal dichalcogenides: interfacial reactions study. 2D Mater, 2015, 2, 014004 doi: 10.1088/2053-1583/2/1/014004
[30]
Azcatl A, McDonnell S, Santosh K C, et al. MoS2 functionalization for ultra-thin atomic layer deposited dielectrics. Appl Phys Lett, 2014, 104, 111601 doi: 10.1063/1.4869149
[31]
Wang J, Li S, Zou X, et al. Integration of high-k oxide on MoS2 by using ozone pretreatment for high-performance MoS2 top-gated transistor with thickness-dependent carrier scattering investigation. Small, 2015, 11, 5932 doi: 10.1002/smll.201501260
[32]
Xiao M, Qiu C, Zhang Z, et al. Atomic-layer-deposition growth of an ultrathin HfO2 film on graphene. ACS Appl Mater Interfaces, 2017, 9, 34050 doi: 10.1021/acsami.7b09408
[33]
Zou X, Wang J, Chiu C H, et al. Interface engineering for high-performance top-gated MoS2 field-effect transistors. Adv Mater, 2014, 26, 6255 doi: 10.1002/adma.201402008
[34]
Takahashi N, Nagashio K. Buffer layer engineering on graphene via various oxidation methods for atomic layer deposition. Appl Phys Express, 2016, 9, 125101 doi: 10.7567/APEX.9.125101
[35]
Illarionov Y Y, Banshchikov A G, Polyushkin D K, et al. Ultrathin calcium fluoride insulators for two-dimensional field-effect transistors. Nat Electron, 2019, 2, 230 doi: 10.1038/s41928-019-0256-8
[36]
Liao L, Lin Y C, Bao M, et al. High-speed graphene transistors with a self-aligned nanowire gate. Nature, 2010, 467, 305 doi: 10.1038/nature09405
[37]
Liao L, Bai J, Qu Y, et al. High-κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors. Proc Natl Acad Sci, 2010, 107, 6711 doi: 10.1073/pnas.0914117107
[38]
Wang X, Tabakman S M, Dai H. Atomic layer deposition of metal oxides on pristine and functionalized graphene. J Am Chem Soc, 2008, 130, 8152 doi: 10.1021/ja8023059
[39]
Alaboson J M, Wang Q H, Emery J D, et al. Seeding atomic layer deposition of high-k dielectrics on epitaxial graphene with organic self-assembled monolayers. ACS Nano, 2011, 5, 5223 doi: 10.1021/nn201414d
[40]
Sangwan V K, Jariwala D, Filippone S A, et al. Quantitatively enhanced reliability and uniformity of high-κ dielectrics on graphene enabled by self-assembled seeding layers. Nano Lett, 2013, 13, 1162 doi: 10.1021/nl3045553
[41]
Park J H, Fathipour S, Kwak I, et al. Atomic layer deposition of Al2O3 on WSe2 functionalized by titanyl phthalocyanine. ACS Nano, 2016, 10, 6888 doi: 10.1021/acsnano.6b02648
[42]
Jiang B, Yang Z Y, Liu X Q, et al. Interface engineering for two-dimensional semiconductor transistors. Nano Today, 2019, 25, 122 doi: 10.1016/j.nantod.2019.02.011
[43]
Kim H G, Leek H B R. Atomic layer deposition on 2D materials. Chem Mater, 2017, 29, 3809 doi: 10.1021/acs.chemmater.6b05103
[44]
Landau L, Lifshitz E. Electrodynamics of continuous media. Oxford: Pergamon, 1960
[45]
Khan A I, Chatterjee K, Wang B, et al. Negative capacitance in a ferroelectric capacitor. Nat Mater, 2015, 7, 182 doi: 10.1038/nmat4148
[46]
Hoffmann M, Pešić M, Chatterjee K, et al. Direct observation of negative capacitance in polycrystalline ferroelectric HfO2. Adv Funct Mater, 2016, 26, 8643 doi: 10.1002/adfm.201602869
[47]
Hoffmann M, Fengler F P, Herzig M, et al. Unveiling the double-well energy landscape in a ferroelectric layer. Nature, 2019, 565, 464 doi: 10.1038/s41586-018-0854-z
[48]
Müller J, Böscke T S, Schröder U, et al. Ferroelectricity in simple binary ZrO2 and HfO2. Nano Lett, 2012, 12(8), 4318 doi: 10.1021/nl302049k
[49]
Cheng C H, Chin A. Low-voltage steep turn-on pMOSFET using ferroelectric high-κ gate dielectric. IEEE Electron Device Lett, 2014, 35, 274 doi: 10.1109/LED.2013.2291560
[50]
Lee M H, Fan S T, Tang C H, et al. Physical thickness 1.x nm ferroelectric HfZrO x negative capacitance FETs. IEEE International Electron Devices Meeting (IEDM), 2016, 12.1.1
[51]
Li C C, Chang-Liao K S, Liu L J, et al. Improved electrical characteristics of Ge MOS devices with high oxidation state in HfGeO x interfacial layer formed by in situ desorption. IEEE Electron Device Lett, 2014, 35, 509 doi: 10.1109/LED.2014.2310636
[52]
Zhou J, Han G, Li, Q, et al. Ferroelectric HfZrO x Ge and GeSn PMOSFETs with sub-60 mV/decade subthreshold swing, negligible hysteresis, and improved IDS. IEEE International Electron Devices Meeting (IEDM), 2016, 12, 12.2.1
[53]
Lee M H, Chen P G, Liu C, et al. Prospects for ferroelectric HfZrO x FETs with experimentally CET = 0.98 nm, SS for = 42 mV/dec, SSrev = 28 mV/dec, switch-off < 0.2 V, and hysteresis-free strategies. IEEE International Electron Devices Meeting (IEDM), 2015, 22.5.1
[54]
Si M, Jiang C, Su C J, et al. Sub-60 mV/dec ferroelectric HZO MoS2 negative capacitance field-effect transistor with internal metal gate: the role of parasitic capacitance. IEEE International Electron Devices Meeting (IEDM), 2017, 23.5.1
[55]
McGuire F A, Lin Y C, Price K, et al. Sustained sub-60 mV/decade switching via the negative capacitance effect in MoS2 transistors. Nano Lett, 2017, 17, 4801 doi: 10.1021/acs.nanolett.7b01584
[56]
Si M, Jiang C, Chung W, et al. Steep-slope WSe2 negative capacitance field-effect transistor. Nano Lett, 2018, 18, 6 doi: 10.1021/acs.nanolett.8b00816
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    Received: 30 July 2019 Revised: 14 August 2019 Online: Accepted Manuscript: 19 August 2019Uncorrected proof: 21 August 2019Published: 01 September 2019

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      Article Navigation >  Journal of Semiconductors  > 2019  >  40(9): 091002
      Weisheng Li, Hongkai Ning, Zhihao Yu, Yi Shi, Xinran Wang. Reducing the power consumption of two-dimensional logic transistors[J]. Journal of Semiconductors, 2019, 40(9): 091002. doi: 10.1088/1674-4926/40/9/091002 ****W S Li, H K Ning, Z H Yu, Y Shi, X R Wang, Reducing the power consumption of two-dimensional logic transistors[J]. J. Semicond., 2019, 40(9): 091002. doi: 10.1088/1674-4926/40/9/091002.
      Citation:
      Weisheng Li, Hongkai Ning, Zhihao Yu, Yi Shi, Xinran Wang. Reducing the power consumption of two-dimensional logic transistors[J]. Journal of Semiconductors, 2019, 40(9): 091002. doi: 10.1088/1674-4926/40/9/091002 ****
      W S Li, H K Ning, Z H Yu, Y Shi, X R Wang, Reducing the power consumption of two-dimensional logic transistors[J]. J. Semicond., 2019, 40(9): 091002. doi: 10.1088/1674-4926/40/9/091002.
      shu

      Reducing the power consumption of two-dimensional logic transistors

      DOI: 10.1088/1674-4926/40/9/091002

      • National Laboratory of Solid State Microstructures, School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093, China

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