Strict non-blocking four-port optical router for mesh photonic network-on-chip

Yuhao Xia; Shanglin Yang; Jiaqi Niu; Xin Fu; Lin Yang

doi:10.1088/1674-4926/43/9/092301

J. Semicond. > 2022, Volume 43 > Issue 9 > 092301, doi: 10.1088/1674-4926/43/9/092301

ARTICLES

Strict non-blocking four-port optical router for mesh photonic network-on-chip

Yuhao Xia^{1, 2}, Shanglin Yang^{1, 2}, Jiaqi Niu^{1, 2}, Xin Fu^{1, 2} and Lin Yang^{1, 2,}

+ Author Affiliations

Corresponding author: Lin Yang, oip@semi.ac.cn

Abstract: We report a strict non-blocking four-port optical router that is used for a mesh photonic network-on-chip on a silicon-on-insulator platform. The router consists of eight silicon microring switches that are tuned by the thermo-optic effect. For each tested rousting state, the signal-to-noise ratio of the optical router is larger than 13.8 dB at the working wavelength. The routing functionality of the device is verified. We perform 40 Gbps nonreturn to zero code data transmission on its 12 optical links. Meanwhile, data transmission using wavelength division multiplexing on eight channels in the C band (from 1525 to 1565 nm) has been adopted to increase the communication capacity. The optical router’s average energy efficiency is 25.52 fJ/bit. The rising times (10% to 90%) of the eight optical switch elements are less than 10 µs and the falling times (90%–10%) are less than 20 µs.

Key words: optical router, microring optical switch, silicon photonics, optical interconnect

References

[1]	Beausoleil R G, Kuekes P J, Snider G S, et al. Nanoelectronic and nanophotonic interconnect. Proc IEEE, 2007, 96(2), 230 doi: 10.1109/JPROC.2007.911057
[2]	Miller D A B. Device requirements for optical interconnects to silicon chips. Proc IEEE, 2009, 97, 1166 doi: 10.1109/JPROC.2009.2014298
[3]	Batten C, Joshi A, Orcutt J, et al. Building manycore processor-to-DRAM networks with monolithic silicon photonics. 16th IEEE Symposium on High Performance Interconnects, 2008 doi: 10.1109/MM.2009.60
[4]	Gu H X, Xu J, Zhang W. A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip. Design, Automation & Test in Europe Conference & Exhibition, 2009 doi: 10.1109/DATE.2009.5090624
[5]	Joshi A, Batten C, Kwon Y J, et al. Silicon-photonic clos networks for global on-chip communication. 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009 doi: 10.1109/NOCS.2009.5071460
[6]	Gu H X, Mo K H, Xu J, et al. A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip. IEEE Computer Society Annual Symposium on VLSI, 2009 doi: 10.1109/ISVLSI.2009.19
[7]	Sherwood-Droz N, Wang H, Chen L, et al. Optical 4 × 4 hitless silicon router for optical Networks-on-Chip (NoC). Opt Express, 2008, 16(20), 15915 doi: 10.1364/OE.16.015915
[8]	Kamierczak A, Bogaerts W, Drouard E, et al. Highly integrated optical 4 × 4 crossbar in Silicon-on-Insulator technology. IEEE J Lightwave Technol, 2009, 27(16), 3317 doi: 10.1109/JLT.2008.2010462
[9]	Ji R Q, Yang L, Zhang L, et al. Five-port optical router for photonic networks-on-chip. Opt Express, 2011, 19(21), 20258 doi: 10.1364/OE.19.020258
[10]	Ye Y, Wu X W, Xu J, et al. Holistic comparison of optical routers for chip multiprocessors. IEEE International Conference on Anti-counterfeiting, Security, and Identification, 2012 doi: 10.1109/ICASID.2012.6325348
[11]	Chan J, Biberman A, Lee B G, et al. Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications. 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society (LEOS 2008), 2008 doi: 10.1109/LEOS.2008.4688609
[12]	Renani N B, Yaghoubi E, Sadehnezhad N, et al. NLR-OP: a high-performance optical router based on North-Last turning model for multicore processors. J Supercomput, 2022, 78(6), 2442 doi: 10.1007/s11227-021-03920-3
[13]	Dang P P, Li C T, Zheng W X, et al. Non-blocking four-port optical router based on thermooptic silicon microrings. Optoelectron Lett, 2016, 12(4), 268 doi: 10.1007/s11801-016-6105-3
[14]	Rhee H W, You J B, Yoon H, et al. 32 Gbps data transmission with 2D beam-steering using a silicon optical phased array. IEEE Photonics Technol Lett, 2020, 32(13), 803 doi: 10.1109/LPT.2020.2998162
[15]	Jia H, Zhou T, Yang S, et al. Five-port non-blocking silicon optical router based on mode-selective property. 18th International Conference on Optical Communications and Networks (ICOCN), 2019, 1 doi: 10.1109/ICOCN.2019.8934430
[16]	Geng M, Tang Z, Chang K, et al. N-port strictly non-blocking optical router based on Mach-Zehnder optical switch for photonic networks-on-chip. Opt Commun, 2017, 383, 472 doi: 10.1016/j.optcom.2016.09.023
[17]	Xia L I, Jiang X Q, Wang X F. A 4 × 4 non-blocking wavelength selective router based on cascaded two-ring resonators. J Optoelectron Laser, 2019, 30(7), 678
[18]	Surenkhorol T, Kishikawa H, Goto N. Integrated-optic circuit for optical 8QAM coded label recognition in photonic router. Integrated Photonics Research, Silicon & Nanophotonics, 2017 doi: 10.1364/IPRSN.2017.JTu4A.26
[19]	Mohamed S, Shahada L, Swillam M. Vertical silicon nanowires based directional coupler optical router. IEEE Photonics Technol Lett, 2018, 30(9), 789 doi: 10.1109/LPT.2018.2815040
[20]	Kalange O A, Ladniya B B, Kothari R R, et al. Design and analysis of five port optical router for optical NoC. 2018 International Conference on Inventive Research in Computing Applications (ICIRCA), 2018 doi: 10.1109/ICIRCA.2018.8597198
[21]	Cheng Q, Liang Y D, Bahadori M, et al. Si/SiN microring-based optical router in switch-and-select topology. 2018 European Conference on Optical Communication (ECOC), 2018 doi: 10.1109/ECOC.2018.8535403
[22]	Ge Z, Zhang L, Wang G, et al. On-chip router elements based on silicon hybrid plasmonic waveguide. IEEE Photonics Technol Lett, 2017, 29(12), 952 doi: 10.1109/LPT.2017.2695081

Fig. 1. (Color online) Schematics of (a) 2D Mesh network of a 16-core CMP and (b) four-port optical router. The blue squares indicate processor cores, yellow dots indicate optical routers, and lines with arrows indicate optical waveguides.

DownLoad: Full-Size Img PowerPoint

Fig. 2. (Color online) Schematics of (a) the optical router and (b) the microring optical switch.

DownLoad: Full-Size Img PowerPoint

Fig. 3. (Color online) Micrograph of the fabricated optical router.

DownLoad: Full-Size Img PowerPoint

Fig. 4. (Color online) Static spectral responses of the microring switch element on its “cross” and “bar” states.

DownLoad: Full-Size Img PowerPoint

Fig. 5. (Color online) Optical SNRs of the four-port optical router in the selected three routing states, which cover its all 12 optical links. Each row represents a single routing state with identical output port in each column. Notation P represents the overall power consumption of each routing state.

DownLoad: Full-Size Img PowerPoint

Fig. 6. (Color online) For all 12 optical links, eyes diagrams at corresponding output ports, 40 Gbps 2³¹–1 PRBS optical signal at wavelength 1547.37 nm is used.

DownLoad: Full-Size Img PowerPoint

Fig. 7. (Color online) WDM data transmission through the optical link Ei → So.

DownLoad: Full-Size Img PowerPoint

Table 1. The 12 optical links of the strict non-blocking four-port optical router.

		Input port
		East	South	West	North
Output port	East	–	→S₇(B) →	→S₈(C) →S₆(B) →S₇(C) →	→S₂(C) →S₅(C) →S₆(C) →S₇(C) →
	South	→ S₁(C) →S₃(C) →S₅(C) →S₈(C) →	–	→S₈(B) →	→S₂(C) →S₅(B) →S₈(C) →
	West	→S₁(C) →S₃(B) →S₂(C) →	→S₇(C) →S₄(C) →S₃(C) →S₂(C) →	–	→S₂(B) →
	North	→S₁(B) →	→S₇(C) →S₄(B) →S₁(C) →	→S₈(C) →S₆(C) →S₄(C) →S₁(C) →	–

DownLoad: CSV

Table 2. States of eight microring optical switches in the three chosen routing states of the four-port optical router which cover 12 optical links (C: in the “cross” state, B: in the “bar” state).

Routing state	Optical links	S₁	S₂	S₃	S₄	S₅	S₆	S₇	S₈
1	E_i → S_o, S_i → W_o, W_i → N_o, N_i → E_o	C	C	C	C	C	C	C	C
2	E_i → W_o, S_i → N_o, W_i → E_o, N_i → S_o	C	C	B	B	B	B	C	C
3	E_i → N_o, S_i → E_o, W_i → S_o, N_i → W_o	B	B	C	C	C	C	B	B

DownLoad: CSV

[1]	Beausoleil R G, Kuekes P J, Snider G S, et al. Nanoelectronic and nanophotonic interconnect. Proc IEEE, 2007, 96(2), 230 doi: 10.1109/JPROC.2007.911057
[2]	Miller D A B. Device requirements for optical interconnects to silicon chips. Proc IEEE, 2009, 97, 1166 doi: 10.1109/JPROC.2009.2014298
[3]	Batten C, Joshi A, Orcutt J, et al. Building manycore processor-to-DRAM networks with monolithic silicon photonics. 16th IEEE Symposium on High Performance Interconnects, 2008 doi: 10.1109/MM.2009.60
[4]	Gu H X, Xu J, Zhang W. A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip. Design, Automation & Test in Europe Conference & Exhibition, 2009 doi: 10.1109/DATE.2009.5090624
[5]	Joshi A, Batten C, Kwon Y J, et al. Silicon-photonic clos networks for global on-chip communication. 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009 doi: 10.1109/NOCS.2009.5071460
[6]	Gu H X, Mo K H, Xu J, et al. A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip. IEEE Computer Society Annual Symposium on VLSI, 2009 doi: 10.1109/ISVLSI.2009.19
[7]	Sherwood-Droz N, Wang H, Chen L, et al. Optical 4 × 4 hitless silicon router for optical Networks-on-Chip (NoC). Opt Express, 2008, 16(20), 15915 doi: 10.1364/OE.16.015915
[8]	Kamierczak A, Bogaerts W, Drouard E, et al. Highly integrated optical 4 × 4 crossbar in Silicon-on-Insulator technology. IEEE J Lightwave Technol, 2009, 27(16), 3317 doi: 10.1109/JLT.2008.2010462
[9]	Ji R Q, Yang L, Zhang L, et al. Five-port optical router for photonic networks-on-chip. Opt Express, 2011, 19(21), 20258 doi: 10.1364/OE.19.020258
[10]	Ye Y, Wu X W, Xu J, et al. Holistic comparison of optical routers for chip multiprocessors. IEEE International Conference on Anti-counterfeiting, Security, and Identification, 2012 doi: 10.1109/ICASID.2012.6325348
[11]	Chan J, Biberman A, Lee B G, et al. Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications. 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society (LEOS 2008), 2008 doi: 10.1109/LEOS.2008.4688609
[12]	Renani N B, Yaghoubi E, Sadehnezhad N, et al. NLR-OP: a high-performance optical router based on North-Last turning model for multicore processors. J Supercomput, 2022, 78(6), 2442 doi: 10.1007/s11227-021-03920-3
[13]	Dang P P, Li C T, Zheng W X, et al. Non-blocking four-port optical router based on thermooptic silicon microrings. Optoelectron Lett, 2016, 12(4), 268 doi: 10.1007/s11801-016-6105-3
[14]	Rhee H W, You J B, Yoon H, et al. 32 Gbps data transmission with 2D beam-steering using a silicon optical phased array. IEEE Photonics Technol Lett, 2020, 32(13), 803 doi: 10.1109/LPT.2020.2998162
[15]	Jia H, Zhou T, Yang S, et al. Five-port non-blocking silicon optical router based on mode-selective property. 18th International Conference on Optical Communications and Networks (ICOCN), 2019, 1 doi: 10.1109/ICOCN.2019.8934430
[16]	Geng M, Tang Z, Chang K, et al. N-port strictly non-blocking optical router based on Mach-Zehnder optical switch for photonic networks-on-chip. Opt Commun, 2017, 383, 472 doi: 10.1016/j.optcom.2016.09.023
[17]	Xia L I, Jiang X Q, Wang X F. A 4 × 4 non-blocking wavelength selective router based on cascaded two-ring resonators. J Optoelectron Laser, 2019, 30(7), 678
[18]	Surenkhorol T, Kishikawa H, Goto N. Integrated-optic circuit for optical 8QAM coded label recognition in photonic router. Integrated Photonics Research, Silicon & Nanophotonics, 2017 doi: 10.1364/IPRSN.2017.JTu4A.26
[19]	Mohamed S, Shahada L, Swillam M. Vertical silicon nanowires based directional coupler optical router. IEEE Photonics Technol Lett, 2018, 30(9), 789 doi: 10.1109/LPT.2018.2815040
[20]	Kalange O A, Ladniya B B, Kothari R R, et al. Design and analysis of five port optical router for optical NoC. 2018 International Conference on Inventive Research in Computing Applications (ICIRCA), 2018 doi: 10.1109/ICIRCA.2018.8597198
[21]	Cheng Q, Liang Y D, Bahadori M, et al. Si/SiN microring-based optical router in switch-and-select topology. 2018 European Conference on Optical Communication (ECOC), 2018 doi: 10.1109/ECOC.2018.8535403
[22]	Ge Z, Zhang L, Wang G, et al. On-chip router elements based on silicon hybrid plasmonic waveguide. IEEE Photonics Technol Lett, 2017, 29(12), 952 doi: 10.1109/LPT.2017.2695081

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Received: 14 February 2022 Revised: 29 March 2022 Online: Accepted Manuscript: 19 May 2022Uncorrected proof: 23 May 2022Published: 02 September 2022

Article Navigation > Journal of Semiconductors > 2022 > 43(9): 092301

Yuhao Xia, Shanglin Yang, Jiaqi Niu, Xin Fu, Lin Yang. Strict non-blocking four-port optical router for mesh photonic network-on-chip[J]. Journal of Semiconductors, 2022, 43(9): 092301. doi: 10.1088/1674-4926/43/9/092301 Y H Xia, S L Yang, J Q Niu, X Fu, L Yang. Strict non-blocking four-port optical router for mesh photonic network-on-chip[J]. J. Semicond, 2022, 43(9): 092301. doi: 10.1088/1674-4926/43/9/092301Export: BibTex EndNote

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Yuhao Xia, Shanglin Yang, Jiaqi Niu, Xin Fu, Lin Yang. Strict non-blocking four-port optical router for mesh photonic network-on-chip[J]. Journal of Semiconductors, 2022, 43(9): 092301. doi: 10.1088/1674-4926/43/9/092301

Y H Xia, S L Yang, J Q Niu, X Fu, L Yang. Strict non-blocking four-port optical router for mesh photonic network-on-chip[J]. J. Semicond, 2022, 43(9): 092301. doi: 10.1088/1674-4926/43/9/092301

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Y H Xia, S L Yang, J Q Niu, X Fu, L Yang. Strict non-blocking four-port optical router for mesh photonic network-on-chip[J]. J. Semicond, 2022, 43(9): 092301. doi: 10.1088/1674-4926/43/9/092301

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Strict non-blocking four-port optical router for mesh photonic network-on-chip

doi: 10.1088/1674-4926/43/9/092301

Yuhao Xia^{1, 2},
Shanglin Yang^{1, 2},
Jiaqi Niu^{1, 2},
Xin Fu^{1, 2},
Lin Yang^{1, 2,}

1.
Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China
2.
College of Materials Science and Opto-Electronic Technology, University of Chinese Academy of Sciences, Beijing 101408, China

More Information

Author Bio:
Yuhao Xia was born in 1990. He received the B.S. degree in electronic engineering from Nankai University, Tianjin, China, in 2013. He is currently pursuing the Ph.D. in microelectronics and solid state electronics in ISCAS. His research interest is silicon-based optical router for optical interconnect

Lin Yang received his Ph.D. degree in microelectronics and solid state electronics from Institute of Semiconductors, Chinese Academy of Sciences (ISCAS), Beijing, China, in 2003. From 2003 to 2007, he was a postdoctoral scholar at Hokkaido University's Research Center for Integrated Quantum Electronics in Sapporo, Japan. He is presently a professor at Institute of Semiconductors, Chinese Academy of Sciences. His current research focuses on silicon photonic devices for optical interconnect, optical computing, and optical communication. He has been the author or coauthor over 100 peer-reviewed scientific journal publications
Corresponding author: oip@semi.ac.cn
Received Date: 2022-02-14
Revised Date: 2022-03-29

Available Online: 2022-05-19

Abstract

Abstract

We report a strict non-blocking four-port optical router that is used for a mesh photonic network-on-chip on a silicon-on-insulator platform. The router consists of eight silicon microring switches that are tuned by the thermo-optic effect. For each tested rousting state, the signal-to-noise ratio of the optical router is larger than 13.8 dB at the working wavelength. The routing functionality of the device is verified. We perform 40 Gbps nonreturn to zero code data transmission on its 12 optical links. Meanwhile, data transmission using wavelength division multiplexing on eight channels in the C band (from 1525 to 1565 nm) has been adopted to increase the communication capacity. The optical router’s average energy efficiency is 25.52 fJ/bit. The rising times (10% to 90%) of the eight optical switch elements are less than 10 µs and the falling times (90%–10%) are less than 20 µs.
- optical router,
- microring optical switch,
- silicon photonics,
- optical interconnect

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References(22)

References

[1]	Beausoleil R G, Kuekes P J, Snider G S, et al. Nanoelectronic and nanophotonic interconnect. Proc IEEE, 2007, 96(2), 230 doi: 10.1109/JPROC.2007.911057
[2]	Miller D A B. Device requirements for optical interconnects to silicon chips. Proc IEEE, 2009, 97, 1166 doi: 10.1109/JPROC.2009.2014298
[3]	Batten C, Joshi A, Orcutt J, et al. Building manycore processor-to-DRAM networks with monolithic silicon photonics. 16th IEEE Symposium on High Performance Interconnects, 2008 doi: 10.1109/MM.2009.60
[4]	Gu H X, Xu J, Zhang W. A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip. Design, Automation & Test in Europe Conference & Exhibition, 2009 doi: 10.1109/DATE.2009.5090624
[5]	Joshi A, Batten C, Kwon Y J, et al. Silicon-photonic clos networks for global on-chip communication. 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009 doi: 10.1109/NOCS.2009.5071460
[6]	Gu H X, Mo K H, Xu J, et al. A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip. IEEE Computer Society Annual Symposium on VLSI, 2009 doi: 10.1109/ISVLSI.2009.19
[7]	Sherwood-Droz N, Wang H, Chen L, et al. Optical 4 × 4 hitless silicon router for optical Networks-on-Chip (NoC). Opt Express, 2008, 16(20), 15915 doi: 10.1364/OE.16.015915
[8]	Kamierczak A, Bogaerts W, Drouard E, et al. Highly integrated optical 4 × 4 crossbar in Silicon-on-Insulator technology. IEEE J Lightwave Technol, 2009, 27(16), 3317 doi: 10.1109/JLT.2008.2010462
[9]	Ji R Q, Yang L, Zhang L, et al. Five-port optical router for photonic networks-on-chip. Opt Express, 2011, 19(21), 20258 doi: 10.1364/OE.19.020258
[10]	Ye Y, Wu X W, Xu J, et al. Holistic comparison of optical routers for chip multiprocessors. IEEE International Conference on Anti-counterfeiting, Security, and Identification, 2012 doi: 10.1109/ICASID.2012.6325348
[11]	Chan J, Biberman A, Lee B G, et al. Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications. 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society (LEOS 2008), 2008 doi: 10.1109/LEOS.2008.4688609
[12]	Renani N B, Yaghoubi E, Sadehnezhad N, et al. NLR-OP: a high-performance optical router based on North-Last turning model for multicore processors. J Supercomput, 2022, 78(6), 2442 doi: 10.1007/s11227-021-03920-3
[13]	Dang P P, Li C T, Zheng W X, et al. Non-blocking four-port optical router based on thermooptic silicon microrings. Optoelectron Lett, 2016, 12(4), 268 doi: 10.1007/s11801-016-6105-3
[14]	Rhee H W, You J B, Yoon H, et al. 32 Gbps data transmission with 2D beam-steering using a silicon optical phased array. IEEE Photonics Technol Lett, 2020, 32(13), 803 doi: 10.1109/LPT.2020.2998162
[15]	Jia H, Zhou T, Yang S, et al. Five-port non-blocking silicon optical router based on mode-selective property. 18th International Conference on Optical Communications and Networks (ICOCN), 2019, 1 doi: 10.1109/ICOCN.2019.8934430
[16]	Geng M, Tang Z, Chang K, et al. N-port strictly non-blocking optical router based on Mach-Zehnder optical switch for photonic networks-on-chip. Opt Commun, 2017, 383, 472 doi: 10.1016/j.optcom.2016.09.023
[17]	Xia L I, Jiang X Q, Wang X F. A 4 × 4 non-blocking wavelength selective router based on cascaded two-ring resonators. J Optoelectron Laser, 2019, 30(7), 678
[18]	Surenkhorol T, Kishikawa H, Goto N. Integrated-optic circuit for optical 8QAM coded label recognition in photonic router. Integrated Photonics Research, Silicon & Nanophotonics, 2017 doi: 10.1364/IPRSN.2017.JTu4A.26
[19]	Mohamed S, Shahada L, Swillam M. Vertical silicon nanowires based directional coupler optical router. IEEE Photonics Technol Lett, 2018, 30(9), 789 doi: 10.1109/LPT.2018.2815040
[20]	Kalange O A, Ladniya B B, Kothari R R, et al. Design and analysis of five port optical router for optical NoC. 2018 International Conference on Inventive Research in Computing Applications (ICIRCA), 2018 doi: 10.1109/ICIRCA.2018.8597198
[21]	Cheng Q, Liang Y D, Bahadori M, et al. Si/SiN microring-based optical router in switch-and-select topology. 2018 European Conference on Optical Communication (ECOC), 2018 doi: 10.1109/ECOC.2018.8535403
[22]	Ge Z, Zhang L, Wang G, et al. On-chip router elements based on silicon hybrid plasmonic waveguide. IEEE Photonics Technol Lett, 2017, 29(12), 952 doi: 10.1109/LPT.2017.2695081

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