SEMICONDUCTOR INTEGRATED CIRCUITS

Security strategy of powered-off SRAM for resisting physical attack to data remanence

Yu Kai, Zou Xuecheng, Yu Guoyi and Wang Weixu

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Abstract: This paper presents a security strategy for resisting a physical attack utilizing data remanence in powered-off static random access memory (SRAM). Based on the mechanism of physical attack to data remanence, the strategy intends to erase data remanence in memory cells once the power supply is removed, which disturbs attackers trying to steal the right information. Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional SRAM to realize erase operation. Implemented in 0.25 μm Huahong-NEC CMOS technology, an SRAM exploiting the proposed security strategy shows the erase operation is accomplished within 0.2 μs and data remanence is successfully eliminated. Compared with conventional SRAM, the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.

Key words: SRAM

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    Received: 18 August 2015 Revised: 07 April 2009 Online: Published: 01 September 2009

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      Yu Kai, Zou Xuecheng, Yu Guoyi, Wang Weixu. Security strategy of powered-off SRAM for resisting physical attack to data remanence[J]. Journal of Semiconductors, 2009, 30(9): 095010. doi: 10.1088/1674-4926/30/9/095010 Yu K, Zou X C, Yu G Y, Wang W X. Security strategy of powered-off SRAM for resisting physical attack to data remanence[J]. J. Semicond., 2009, 30(9): 095010. doi: 10.1088/1674-4926/30/9/095010.Export: BibTex EndNote
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      Yu Kai, Zou Xuecheng, Yu Guoyi, Wang Weixu. Security strategy of powered-off SRAM for resisting physical attack to data remanence[J]. Journal of Semiconductors, 2009, 30(9): 095010. doi: 10.1088/1674-4926/30/9/095010

      Yu K, Zou X C, Yu G Y, Wang W X. Security strategy of powered-off SRAM for resisting physical attack to data remanence[J]. J. Semicond., 2009, 30(9): 095010. doi: 10.1088/1674-4926/30/9/095010.
      Export: BibTex EndNote

      Security strategy of powered-off SRAM for resisting physical attack to data remanence

      doi: 10.1088/1674-4926/30/9/095010
      • Received Date: 2015-08-18
      • Accepted Date: 2009-02-18
      • Revised Date: 2009-04-07
      • Published Date: 2009-08-28

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