SEMICONDUCTOR INTEGRATED CIRCUITS

A 100 MS/s 9 bit 0.43 mW SAR ADC with custom capacitor array

Jingjing Wang, Zemin Feng, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu and Junyan Ren

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 Corresponding author: Corresponding author. Email: jxu@fudan.edu.cn

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Abstract: A low power 9 bit 100 MS/s successive approximation register analog-to-digital converter (SAR ADC) with custom capacitor array is presented. A brand-new 3-D MOM unit capacitor is used as the basic capacitor cell of this capacitor array. The unit capacitor has a capacitance of 1 fF. Besides, the advanced capacitor array structure and switch mode decrease the power consumption a lot. To verify the effectiveness of this low power design, the 9 bit 100 MS/s SAR ADC is implemented in TSMC IP9M 65 nm LP CMOS technology. The measurement results demonstrate that this design achieves an effective number of bits (ENOB) of 7.4 bit, a signal-to-noise plus distortion ratio (SNDR) of 46.40 dB and a spurious-free dynamic range (SFDR) of 62.31 dB at 100 MS/s with 1 MHz input. The SAR ADC core occupies an area of 0.030 mm2 and consumes 0.43 mW under a supply voltage of 1.2 V. The figure of merit (FOM) of the SAR ADC achieves 23.75 fJ/conv.

Key words: SAR ADClow powercustom metal-oxide-metal capacitorcapacitor array structure



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Fig. 1.  (a) Traditional structure of 9-bit SAR ADC with bottom-plate sampling. (b) Variation of traditional SAR ADC comparator input voltage during quantization.

Fig. 2.  (a) Advanced structure of 9-bit SAR ADC with bottom-plate sampling. (b) Variation of advanced SAR ADC comparator input voltage during quantization.

Fig. 3.  (a) 3-D view of the brand-new MOM capacitor. (b) Metal layer view of it[[2]].

Fig. 4.  Comparator.

Fig. 5.  (a) Internal clock generation circuit. (b) Sequence diagram of every internal clock.

Fig. 6.  (a) Switch control logic circuit. (b) Diagram of input and output response.

Fig. 7.  Output buffer.

Fig. 8.  (Color online) Die photo and layout diagram of this design.

Fig. 9.  FFT spectrum at 1 MHz input.

Fig. 10.  Static measurement result of DNL and INL.

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Table 1.   Performance summary.

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Table 2.   Comparsion among recent related work.

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    Received: 17 August 2015 Revised: Online: Published: 01 May 2016

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      Jingjing Wang, Zemin Feng, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren. A 100 MS/s 9 bit 0.43 mW SAR ADC with custom capacitor array[J]. Journal of Semiconductors, 2016, 37(5): 055003. doi: 10.1088/1674-4926/37/5/055003 J J Wang, Z M Feng, R J Xu, C X Chen, F Ye, J Xu, J Y Ren. A 100 MS/s 9 bit 0.43 mW SAR ADC with custom capacitor array[J]. J. Semicond., 2016, 37(5): 055003. doi: 10.1088/1674-4926/37/5/055003.Export: BibTex EndNote
      Citation:
      Jingjing Wang, Zemin Feng, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren. A 100 MS/s 9 bit 0.43 mW SAR ADC with custom capacitor array[J]. Journal of Semiconductors, 2016, 37(5): 055003. doi: 10.1088/1674-4926/37/5/055003

      J J Wang, Z M Feng, R J Xu, C X Chen, F Ye, J Xu, J Y Ren. A 100 MS/s 9 bit 0.43 mW SAR ADC with custom capacitor array[J]. J. Semicond., 2016, 37(5): 055003. doi: 10.1088/1674-4926/37/5/055003.
      Export: BibTex EndNote

      A 100 MS/s 9 bit 0.43 mW SAR ADC with custom capacitor array

      doi: 10.1088/1674-4926/37/5/055003
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      Project supported by the National High-Tech Research and Development Program of China (No. 2013AA014101).

      More Information
      • Corresponding author: Corresponding author. Email: jxu@fudan.edu.cn
      • Received Date: 2015-08-17
      • Accepted Date: 2015-10-28
      • Published Date: 2016-01-25

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