Fig. 1.
The block diagram of proposed CCD AFE.
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Jingyu Wang, Zhangming Zhu, Shubin Liu. A 14-bit 40-MHz analog front end for CCD application[J]. Journal of Semiconductors, 2016, 37(6): 065002. doi: 10.1088/1674-4926/37/6/065002
J Y Wang, Z M Zhu, S B Liu. A 14-bit 40-MHz analog front end for CCD application[J]. J. Semicond., 2016, 37(6): 065002. doi: 10.1088/1674-4926/37/6/065002.
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A 14-bit 40-MHz analog front end for CCD application
doi: 10.1088/1674-4926/37/6/065002
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Abstract
A 14-bit, 40-MHz analog front end (AFE) for CCD scanners is analyzed and designed. The proposed system incorporates a digitally controlled wideband variable gain amplifier (VGA) with nearly 42 dB gain range, a correlated double sampler (CDS) with programmable gain functionality, a 14-bit analog-to-digital converter and a programmable timing core. To achieve the maximum dynamic range, the VGA proposed here can linearly amplify the input signal in a gain range from -1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth. A novel CDS takes image information out of noise, and further amplifies the signal accurately in a gain range from 0 to 18 dB in 0.035 dB step. A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity. An internal timing core can provide flexible timing for CCD arrays, CDS and ADC. The proposed AFE was fabricated in SMIC 0.18 μm CMOS process. The whole circuit occupied an active area of 2.8×4.8 mm2 and consumed 360 mW. When the frequency of input signal is 6.069 MHz, and the sampling frequency is 40 MHz, the signal to noise and distortion (SNDR) is 70.3 dB, the effective number of bits is 11.39 bit. -
References
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