A broadband 47-67 GHz LNA with 17.3 dB gain in 65-nm CMOS

Chong Wang; Zhiqun Li; Qin Li; Yang Liu; Zhigong Wang

doi:10.1088/1674-4926/36/10/105010

J. Semicond. > 2015, Volume 36 > Issue 10 > 105010, doi: 10.1088/1674-4926/36/10/105010

SEMICONDUCTOR INTEGRATED CIRCUITS

A broadband 47-67 GHz LNA with 17.3 dB gain in 65-nm CMOS

Chong Wang, Zhiqun Li, Qin Li, Yang Liu and Zhigong Wang

+ Author Affiliations

Abstract: A broadband 47-67 GHz low noise amplifier (LNA) with 17.3 dB gain in 65-nm CMOS technology is proposed.The features of millimeter wave circuits are illustrated first and design methodologies are discussed.The wideband input matching of the LNA was achieved by source inductive degeneration, which is narrowband in the low-GHz range but wideband at millimeter-wave frequencies due to the existence of gate-drain capacitance, C_gd.In order to minimize the noise figure (NF), the LNA used a common-source (CS) structure rather than cascode in the first stage, and the noise matching principle is explored.The last two stages of the LNA used a cascode structure to increase the power gain.Analysis of the gain boost effect of the gate inductor at the common-gate (CG) transistor is also performed.T-shape matching networks between stages are intended to enlarge the bandwidth.All on-chip inductors and transmission lines are modeled and simulated with a 3-dimensional electromagnetic (EM) simulation tool to guarantee the success of the design.Measurement results show that the LNA achieves a maximum gain of 17.3 dB at 60 GHz, while the 3-dB bandwidth is 20 GHz (47-67 GHz), including the interested band of 59-64 GHz, and the minimum noise figure is 4.9 dB at 62 GHz.The LNA absorbs a current of 19 mA from a 1.2 V supply and the chip occupies an area of 900×550 μm² including pads.

Key words: CMOS, 60 GHz, low noise amplifier, wideband, electromagnetic simulation

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Fig. 1. Schematic of the proposed LNA.

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Fig. 2. MOS transistors model with $L_{\rm s}$ and $Z_{\rm d}$.

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Fig. 3. Equivalent input admittance of the gate.

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Fig. 4. NF$_{\rm min}$ of the CS and cascode topology.

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Fig. 5. Cascode topology with gain boosting techniques.

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Fig. 6. CG transistor with gate feedback inductor.

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Fig. 7. Amplifier with an LC inter-stage network.

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Fig. 8. T-shape inter-stage network.

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Fig. 9. Die photograph of the designed LNA.

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Fig. 10. $S_{21}$ and noise figure.

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Fig. 11. Measured and simulated $S_{11}$/$S_{22}$.

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Fig. 12. Power gain versus input power.

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Table 1. Performance summary and comparison.

Parameter	Reference ^[9]	Reference ^[10]	Reference ^[12]	Reference ^[13]	This work
CMOS technology	90 nm	65 nm	90 nm	90 nm	65 nm
Gain (dB)	14.6	18	11.4	15.5	17.3
3 dB BW (GHz)	5	12.2	12.5	8	20
NF (dB)	4.5*	43.9	6.5	4.9
PD (mW)	24	28.8	14.1	86	22.8
FOM (GHz/mW)	2.1	10.7	4.9	0.73	15.2

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Received: 07 June 2015 Revised: Online: Published: 01 October 2015

A broadband 47-67 GHz low noise amplifier (LNA) with 17.3 dB gain in 65-nm CMOS technology is proposed.The features of millimeter wave circuits are illustrated first and design methodologies are discussed.The wideband input matching of the LNA was achieved by source inductive degeneration, which is narrowband in the low-GHz range but wideband at millimeter-wave frequencies due to the existence of gate-drain capacitance, C_gd.In order to minimize the noise figure (NF), the LNA used a common-source (CS) structure rather than cascode in the first stage, and the noise matching principle is explored.The last two stages of the LNA used a cascode structure to increase the power gain.Analysis of the gain boost effect of the gate inductor at the common-gate (CG) transistor is also performed.T-shape matching networks between stages are intended to enlarge the bandwidth.All on-chip inductors and transmission lines are modeled and simulated with a 3-dimensional electromagnetic (EM) simulation tool to guarantee the success of the design.Measurement results show that the LNA achieves a maximum gain of 17.3 dB at 60 GHz, while the 3-dB bandwidth is 20 GHz (47-67 GHz), including the interested band of 59-64 GHz, and the minimum noise figure is 4.9 dB at 62 GHz.The LNA absorbs a current of 19 mA from a 1.2 V supply and the chip occupies an area of 900×550 μm² including pads.

A broadband 47-67 GHz LNA with 17.3 dB gain in 65-nm CMOS

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A broadband 47-67 GHz LNA with 17.3 dB gain in 65-nm CMOS

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