J. Semicond. > 2018, Volume 39 > Issue 3 > 035003, doi:  10.1088/1674-4926/39/3/035003

SEMICONDUCTOR INTEGRATED CIRCUITS

Design and analysis of an energy-efficient O-QPSK coherent IR-UWB transceiver with a 0.52° RMS phase-noise fractional synthesizer

Yutong Ying, Fujiang Lin and Xuefei Bai

+ Author Affiliations

 Corresponding author: Xuefei Bai, Email: baixf@ustc.edu.cn

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Abstract: This paper explores an energy-efficient pulsed ultra-wideband (UWB) radio-frequency (RF) front-end chip fabricated in 0.18-μm CMOS technology, including a transmitter, receiver, and fractional synthesizer. The transmitter adopts a digital offset quadrature phase-shift keying (O-QPSK) modulator and passive direct-phase multiplexing technology, which are energy- and hardware-efficient, to enhance the data rate for a given spectrum. A passive mixer and a capacitor cross-coupled (CCC) source-follower driving amplifier (DA) are also designed for the transmitter to further reduce the low power consumption. For the receiver, a power-aware low-noise amplifier (LNA) and a quadrature mixer are applied. The LNA adopts a CCC boost common-gate amplifier as the input stage, and its current is reused for the second stage to save power. The mixer uses a shared amplification stage for the following passive IQ mixer. Phase noise suppression of the phase-locked loop (PLL) is achieved by utilizing an even-harmonics-nulled series-coupled quadrature oscillator (QVCO) and an in-band noise-aware charge pump (CP) design. The transceiver achieves a measured data rate of 0.8 Gbps with power consumption of 16 mW and 31.5 mW for the transmitter and the receiver, respectively. The optimized integrated phase noise of the PLL is 0.52° at 4.025 GHz.

Key words: IR-UWB, O-QPSK modulation, phase multiplexing, transmitter, receiver, fractional PLL



[1]
IEEE Std., IEEE802.11ad http://standards.ieee.org/ develop/project/802.11ad.html
[2]
Steve LO, Sever I, Ssu-Pin P J, et al. A dual-antenna phased-array UWB transceiver in 0.18 μm CMOS. IEEE J Solid-State Circuits, 2006, 41(12): 2776 doi: 10.1109/JSSC.2006.884803
[3]
Werther O, Cavin M, Schneider A, et al. A fully integrated 14 band, 3.1 to 10.6 GHz 0.13 μm SiGe BiCMOS UWB RF transceiver. IEEE J Solid-State Circuits, 2008, 43(12): 2829 doi: 10.1109/JSSC.2008.2005744
[4]
Sandner C, Derksen S, Draxelmayr D, et al. A wimedia/mboa-compliant cmos rf transceiver for uwb. IEEE J Solid-State Circuits, 2006, 41(12): 2787 doi: 10.1109/JSSC.2006.884804
[5]
Leenaerts D, van de Beek R, Bergervoet J, et al. A 65 nm CMOS inductorless triple band group WiMedia UWB PHY. IEEE J Solid-State Circuits, 2009, 44(12): 3499 doi: 10.1109/JSSC.2009.2032588
[6]
Diao S, Zheng Y, Heng C H. A CMOS ultra low-power and highly efficient UWB-IR transmitter for WPAN applications. IEEE Trans Circuits Syst II, 2009, 56(3): 200 doi: 10.1109/TCSII.2009.2015369
[7]
Crepaldi M, Li C, Fernandes J R, et al. An ultra-wideband impulse-radio transceiver chipset using synchronized-OOK modulation. IEEE J Solid-State Circuits, 2011, 46(10): 2284 doi: 10.1109/JSSC.2011.2161214
[8]
Mercier P P, Daly D C, Chandrakasan A P. An energy-efficient all-digital UWB transmitter employing dual capacitively-coupled pulse-shaping drivers. IEEE J Solid-State Circuits, 2009, 44(6): 1679 doi: 10.1109/JSSC.2009.2020466
[9]
Smaini L, Tinella C, Hélal D, et al. Single-chip CMOS pulse generator for UWB systems. IEEE J Solid-State Circuits, 2006, 41(7): 1551 doi: 10.1109/JSSC.2006.873896
[10]
Xia L, Shao K, Chen H, et al. 0.15-nJ/b 3–5-GHz IR-UWB system with spectrum tunable transmitter and merged-correlator noncoherent receiver. IEEE Trans Microwave Theory Tech, 2011, 59(4): 1147 doi: 10.1109/TMTT.2011.2114193
[11]
Wentzloff D D, Chandrakasan A P. A 47pJ/pulse 3.1 to 5 GHz all-digital UWB transmitter in 90 nm CMOS. IEEE Solid-State Circuits Conference (ISSCC), 2007: 118
[12]
Zhou L, Chen Z, Wang C C, et al. A 2-Gb/s 130-nm CMOS RF-correlation-based IR-UWB transceiver front-end. IEEE Trans Microwave Theory Tech, 2011, 59(4): 1117 doi: 10.1109/TMTT.2011.2114190
[13]
Geng S, Liu D, Li Y, et al. A 13.3 mW 500 Mb/s IR-UWB transceiver with link margin enhancement technique for meter-range communications. IEEE J Solid-State Circuits, 2015, 50(3): 669 doi: 10.1109/JSSC.2015.2393815
[14]
Demirkan M, Spencer R R. A pulse-based ultra-wideband transmitter in 90-nm CMOS for WPANs. IEEE J Solid-State Circuits, 2008, 43(12): 2820 doi: 10.1109/JSSC.2008.2005703
[15]
Verhelst M, Dehaene W. System design of an ultra-low power, low data rate, pulsed UWB receiver in the 0–960 MHz band. IEEE International Conference on Communications (ICC), 2005(4): 2812
[16]
Ryckaert J, Verhelst M, Badaroglu M, et al. A CMOS ultra-wideband receiver for low data-rate communication. IEEE J Solid-State Circuits, 2007, 42(11): 2515 doi: 10.1109/JSSC.2007.907195
[17]
Yin H, Wang Z, Ke L, et al. Monobit digital receivers: design, performance, and application to impulse radio. IEEE Trans Commun, 2010, 58(6): 1695 doi: 10.1109/TCOMM.2010.06.080446
[18]
Singh J, Ponnuru S, Madhow U. Multi-gigabit communication: the ADC bottleneck. IEEE International Conference on Ultra-Wideband (ICUWB), 2009: 22
[19]
Liu Y H, Li C L, Lin T H. A 200-pJ/b MUX-based RF transmitter for implantable multichannel neural recording. IEEE Trans Microwave Theory Tech, 2009, 57(10): 2533 doi: 10.1109/TMTT.2009.2029955
[20]
Wang H, Sun L, Huang L, et al. Design of UWB circuits with inductive peaking technique. IEEE International Conference on Microwave and Millimeter Wave Technology (ICMMT), 2012(1): 1
[21]
Lee H D, Lee K A, Hong S. A wideband CMOS variable gain amplifier with an exponential gain control. IEEE Trans Microwave Theory Tech, 2007, 55(6): 1363 doi: 10.1109/TMTT.2007.896787
[22]
Li C, Lu H, Yutong Y, et al. High performance QVCO design with series coupling in CMOS technology. J Semicond, 2011, 32(11): 115004 doi: 10.1088/1674-4926/32/11/115004
[23]
Hajimiri A, Lee T H. Design issues in CMOS differential LC oscillators. IEEE J Solid-State Circuits, 1999, 34(5): 717 doi: 10.1109/4.760384
[24]
Ismail A, Abidi A A. CMOS differential LC oscillator with suppressed up-converted flicker noise. IEEE International Solid-State Circuits Conference (ISSCC), 2003: 98
[25]
Fanori L, Liscidini A, Castello R. Capacitive degeneration in LC-tank oscillator for DCO fine-frequency tuning. IEEE J Solid-State Circuits, 2010, 45(12): 2737 doi: 10.1109/JSSC.2010.2077190
[26]
Temporiti E, Albasini G, Bietti I, et al. A 700-KHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for wcdma applications. IEEE J Solid-State Circuits, 2004, 39(9): 1446 doi: 10.1109/JSSC.2004.831598
[27]
Lee J S, Keel M S, Lim S I, et al. Charge pump with perfect current matching characteristics in phase-locked loops. Electronics Letters, 2000, 36(23): 1907 doi: 10.1049/el:20001358
[28]
Rhee W, Song B S, Ali A. A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order/spl Delta//spl Sigma/ modulator. IEEE J Solid-State Circuits, 2000, 35(10): 1453 doi: 10.1109/4.871322
[29]
Kim N S, Rabaey J M. A high data-rate energy-efficient triple-channel uwb-based cognitive radio. IEEE J Solid-State Circuits, 2016, 51(4): 809 doi: 10.1109/JSSC.2015.2512934
[30]
Medi A, Namgoong W. A high data-rate energy-efficient interference-tolerant fully integrated CMOS frequency channelized UWB transceiver for impulse radio. IEEE J Solid-State Circuits, 2008, 43(4): 974 doi: 10.1109/JSSC.2008.917513
Fig. 1.  (Color online) QPSK transceiver schematic.

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Fig. 2.  (Color online) O-QPSK modulator.

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Fig. 3.  Transmitting chain.

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Fig. 4.  (Color online) LNA (a) schematic and (b) wideband operation.

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Fig. 5.  Quadrature mixer schematic.

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Fig. 6.  VGA and last stage buffer schematic.

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Fig. 7.  (Color online) QVCO schematic.

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Fig. 8.  (Color online) Simulated oscillation frequency and phase noise at 10 KHz and 1 MHz offset over Cnull sweep.

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Fig. 9.  (Color online) Active transistors’ noise influence at (a) 10 kHz and (b) 1 MHz offset.

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Fig. 10.  (Color online) (a) OP feedback-based charge pump and (b) bias circuit for the OP.

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Fig. 11.  (Color online) (a) Simulated current matching and (b) output noise of the charge pump.

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Fig. 12.  (Color online) Chip photograph.

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Fig. 13.  (Color online) Measured (a) phase noise, (b) reference spur, and (c) wideband spurs at fo/2.

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Fig. 14.  (Color online) Measured waveform at (a) 250 MHz PRF and (b) 500 MHz PRF.

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Fig. 15.  (Color online) Simulated four-states transmitter output pulses with 4.025 GHz LO and 1 ns pulse duration.

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Fig. 16.  (Color online) (a) Measured transmitter output spectrum, (b) simulated spectra with 1 ns and 2 ns pulse width, (c) simulated spectra for pulse train with random BPSK/QPSK/8PSK data.

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Fig. 17.  (Color online) Measured receiver gain and noise versus IF frequency.

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Fig. 18.  (Color online) Receiver output IQ waveforms with 4.5-GHz sinusoid input. The phase difference between the I- and Q-channel measures 24.7%, i.e., 2.7°.

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Fig. 19.  (Color online) Loop-back waveform test of the transceiver: (a) 125-MHz PRF and (b) 400-MHz PRF.

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Table 1.   Performance summary and comparison.

Parameter This work JSSC'15 JSSC'16 JSSC'08
CMOS technology (nm) 180 65 65 180
VDD (V) 1.8 1 1.2 1.8
Frequency band (GHz) 3～5 7.25～9.5 3～10 3～5
Modulation QSPK OOK BPSK BPSK
Data rate (Gbps) 1 TX 0.8 TRX 0.5 TX 0.25 TRX 1 TX 1 TRX 1 TX 1 TRX
TX Pulse width (ns) 1 NA 3 ～0.5
Pulse amplitude (Vpp) 0.18 0.4 0.16 0.7
Maximum PRF (MHz) 500 500 333* 1000
Power consumption (mW) 16.0 6.9 21.4–22.6 108
RX Gain (dB) 26～64 NA 15.4～67.6 82
Noise figure (dB) 52～1.5 NA 6.9～7.6 4.5
Maximum PRF (MHz) 400 500 333 1000
Power consumption (mW) 31.5 5.9 17.3～20.9 66.6
LO Freq (GIIz) 4.025 8.645 10.56 4
VCO PN @l MHz (dBc/Hz) –125 –105.6 NA –119
PLL PN @l MHz (dBc/Hz) –122.8 NA –92.38 NA
In band PN (dBc/Hz) –93 NA –92.38 NA
RMS Phase noise (ps) 0.73 NA NA NA
Reference spur (dBc) –77.2 NA –59 NA
Power consumption (mW) 36 2.2 10.5～29.4 32.4
Enegry efficiency (pJ/bit) 104 26 59.7–102.2 206
* Each channel has fixed PRF of 333 MHz, three channels used to achieve effective 1 GHz PRF.
DownLoad: CSV
[1]
IEEE Std., IEEE802.11ad http://standards.ieee.org/ develop/project/802.11ad.html
[2]
Steve LO, Sever I, Ssu-Pin P J, et al. A dual-antenna phased-array UWB transceiver in 0.18 μm CMOS. IEEE J Solid-State Circuits, 2006, 41(12): 2776 doi: 10.1109/JSSC.2006.884803
[3]
Werther O, Cavin M, Schneider A, et al. A fully integrated 14 band, 3.1 to 10.6 GHz 0.13 μm SiGe BiCMOS UWB RF transceiver. IEEE J Solid-State Circuits, 2008, 43(12): 2829 doi: 10.1109/JSSC.2008.2005744
[4]
Sandner C, Derksen S, Draxelmayr D, et al. A wimedia/mboa-compliant cmos rf transceiver for uwb. IEEE J Solid-State Circuits, 2006, 41(12): 2787 doi: 10.1109/JSSC.2006.884804
[5]
Leenaerts D, van de Beek R, Bergervoet J, et al. A 65 nm CMOS inductorless triple band group WiMedia UWB PHY. IEEE J Solid-State Circuits, 2009, 44(12): 3499 doi: 10.1109/JSSC.2009.2032588
[6]
Diao S, Zheng Y, Heng C H. A CMOS ultra low-power and highly efficient UWB-IR transmitter for WPAN applications. IEEE Trans Circuits Syst II, 2009, 56(3): 200 doi: 10.1109/TCSII.2009.2015369
[7]
Crepaldi M, Li C, Fernandes J R, et al. An ultra-wideband impulse-radio transceiver chipset using synchronized-OOK modulation. IEEE J Solid-State Circuits, 2011, 46(10): 2284 doi: 10.1109/JSSC.2011.2161214
[8]
Mercier P P, Daly D C, Chandrakasan A P. An energy-efficient all-digital UWB transmitter employing dual capacitively-coupled pulse-shaping drivers. IEEE J Solid-State Circuits, 2009, 44(6): 1679 doi: 10.1109/JSSC.2009.2020466
[9]
Smaini L, Tinella C, Hélal D, et al. Single-chip CMOS pulse generator for UWB systems. IEEE J Solid-State Circuits, 2006, 41(7): 1551 doi: 10.1109/JSSC.2006.873896
[10]
Xia L, Shao K, Chen H, et al. 0.15-nJ/b 3–5-GHz IR-UWB system with spectrum tunable transmitter and merged-correlator noncoherent receiver. IEEE Trans Microwave Theory Tech, 2011, 59(4): 1147 doi: 10.1109/TMTT.2011.2114193
[11]
Wentzloff D D, Chandrakasan A P. A 47pJ/pulse 3.1 to 5 GHz all-digital UWB transmitter in 90 nm CMOS. IEEE Solid-State Circuits Conference (ISSCC), 2007: 118
[12]
Zhou L, Chen Z, Wang C C, et al. A 2-Gb/s 130-nm CMOS RF-correlation-based IR-UWB transceiver front-end. IEEE Trans Microwave Theory Tech, 2011, 59(4): 1117 doi: 10.1109/TMTT.2011.2114190
[13]
Geng S, Liu D, Li Y, et al. A 13.3 mW 500 Mb/s IR-UWB transceiver with link margin enhancement technique for meter-range communications. IEEE J Solid-State Circuits, 2015, 50(3): 669 doi: 10.1109/JSSC.2015.2393815
[14]
Demirkan M, Spencer R R. A pulse-based ultra-wideband transmitter in 90-nm CMOS for WPANs. IEEE J Solid-State Circuits, 2008, 43(12): 2820 doi: 10.1109/JSSC.2008.2005703
[15]
Verhelst M, Dehaene W. System design of an ultra-low power, low data rate, pulsed UWB receiver in the 0–960 MHz band. IEEE International Conference on Communications (ICC), 2005(4): 2812
[16]
Ryckaert J, Verhelst M, Badaroglu M, et al. A CMOS ultra-wideband receiver for low data-rate communication. IEEE J Solid-State Circuits, 2007, 42(11): 2515 doi: 10.1109/JSSC.2007.907195
[17]
Yin H, Wang Z, Ke L, et al. Monobit digital receivers: design, performance, and application to impulse radio. IEEE Trans Commun, 2010, 58(6): 1695 doi: 10.1109/TCOMM.2010.06.080446
[18]
Singh J, Ponnuru S, Madhow U. Multi-gigabit communication: the ADC bottleneck. IEEE International Conference on Ultra-Wideband (ICUWB), 2009: 22
[19]
Liu Y H, Li C L, Lin T H. A 200-pJ/b MUX-based RF transmitter for implantable multichannel neural recording. IEEE Trans Microwave Theory Tech, 2009, 57(10): 2533 doi: 10.1109/TMTT.2009.2029955
[20]
Wang H, Sun L, Huang L, et al. Design of UWB circuits with inductive peaking technique. IEEE International Conference on Microwave and Millimeter Wave Technology (ICMMT), 2012(1): 1
[21]
Lee H D, Lee K A, Hong S. A wideband CMOS variable gain amplifier with an exponential gain control. IEEE Trans Microwave Theory Tech, 2007, 55(6): 1363 doi: 10.1109/TMTT.2007.896787
[22]
Li C, Lu H, Yutong Y, et al. High performance QVCO design with series coupling in CMOS technology. J Semicond, 2011, 32(11): 115004 doi: 10.1088/1674-4926/32/11/115004
[23]
Hajimiri A, Lee T H. Design issues in CMOS differential LC oscillators. IEEE J Solid-State Circuits, 1999, 34(5): 717 doi: 10.1109/4.760384
[24]
Ismail A, Abidi A A. CMOS differential LC oscillator with suppressed up-converted flicker noise. IEEE International Solid-State Circuits Conference (ISSCC), 2003: 98
[25]
Fanori L, Liscidini A, Castello R. Capacitive degeneration in LC-tank oscillator for DCO fine-frequency tuning. IEEE J Solid-State Circuits, 2010, 45(12): 2737 doi: 10.1109/JSSC.2010.2077190
[26]
Temporiti E, Albasini G, Bietti I, et al. A 700-KHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for wcdma applications. IEEE J Solid-State Circuits, 2004, 39(9): 1446 doi: 10.1109/JSSC.2004.831598
[27]
Lee J S, Keel M S, Lim S I, et al. Charge pump with perfect current matching characteristics in phase-locked loops. Electronics Letters, 2000, 36(23): 1907 doi: 10.1049/el:20001358
[28]
Rhee W, Song B S, Ali A. A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order/spl Delta//spl Sigma/ modulator. IEEE J Solid-State Circuits, 2000, 35(10): 1453 doi: 10.1109/4.871322
[29]
Kim N S, Rabaey J M. A high data-rate energy-efficient triple-channel uwb-based cognitive radio. IEEE J Solid-State Circuits, 2016, 51(4): 809 doi: 10.1109/JSSC.2015.2512934
[30]
Medi A, Namgoong W. A high data-rate energy-efficient interference-tolerant fully integrated CMOS frequency channelized UWB transceiver for impulse radio. IEEE J Solid-State Circuits, 2008, 43(4): 974 doi: 10.1109/JSSC.2008.917513

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    Received: 07 May 2017 Revised: 15 August 2017 Online: Uncorrected proof: 24 January 2018Published: 01 March 2018

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      Article Navigation >  Journal of Semiconductors  > 2018  >  39(3): 035003
      Yutong Ying, Fujiang Lin, Xuefei Bai. Design and analysis of an energy-efficient O-QPSK coherent IR-UWB transceiver with a 0.52° RMS phase-noise fractional synthesizer[J]. Journal of Semiconductors, 2018, 39(3): 035003. doi:  10.1088/1674-4926/39/3/035003 Y T Ying, F J Lin, X F Bai. Design and analysis of an energy-efficient O-QPSK coherent IR-UWB transceiver with a 0.52° RMS phase-noise fractional synthesizer[J]. J. Semicond., 2018, 39(3): 035003. doi:  10.1088/1674-4926/39/3/035003.Export: BibTex EndNote
      Citation:
      Yutong Ying, Fujiang Lin, Xuefei Bai. Design and analysis of an energy-efficient O-QPSK coherent IR-UWB transceiver with a 0.52° RMS phase-noise fractional synthesizer[J]. Journal of Semiconductors, 2018, 39(3): 035003. doi:  10.1088/1674-4926/39/3/035003

      Y T Ying, F J Lin, X F Bai. Design and analysis of an energy-efficient O-QPSK coherent IR-UWB transceiver with a 0.52° RMS phase-noise fractional synthesizer[J]. J. Semicond., 2018, 39(3): 035003. doi:  10.1088/1674-4926/39/3/035003.
      Export: BibTex EndNote
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      Design and analysis of an energy-efficient O-QPSK coherent IR-UWB transceiver with a 0.52° RMS phase-noise fractional synthesizer

      doi:  10.1088/1674-4926/39/3/035003

      • Department of Electronics Science and Technology, University of Science and Technology of China, Hefei 230027, China

      Funds:

      Project supported by the National Science and Technology Major Project of China (No. 2011ZX03004-002-01).

      More Information
      • Corresponding author: Email: baixf@ustc.edu.cn
      • Received Date: 2017-05-07
      • Revised Date: 2017-08-15
        • Available Online: 2018-03-01
      • Published Date: 2018-03-01

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