Fig. 1.
Schematic diagram of GaAs MOSFET with stack high-$k$ gate dielectric.
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| Citation: |
Chaowen Liu, Jingping Xu, Lu Liu, Hanhan Lu, Yuan Huang. A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric[J]. Journal of Semiconductors, 2016, 37(2): 024004. doi: 10.1088/1674-4926/37/2/024004
C W Liu, J P Xu, L Liu, H H Lu, Y Huang. A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric[J]. J. Semicond., 2016, 37(2): 024004. doi: 10.1088/1674-4926/37/2/024004.
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A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric
doi: 10.1088/1674-4926/37/2/024004
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Abstract
A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored. -
References
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