J. Semicond. > 2015, Volume 36 > Issue 11 > 115006, doi: 10.1088/1674-4926/36/11/115006
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SEMICONDUCTOR INTEGRATED CIRCUITS

Single event transient pulse width measurement of 65-nm bulk CMOS circuits

Suge Yue1, 2, , Xiaolin Zhang1 and Xinyuan Zhao2

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 Corresponding author: Yue Suge, Email: yuesg9999@163.com

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Abstract: Heavy ion results of a 65-nm CMOS SET pulse width testchip are given. The influences of device threshold voltage, temperature and well separation on pulse width are discussed. Experimental data implied that the low device threshold, high temperature and well speraration would contribute to wider SET. The multi-peak phenomenon in the distribution of SET pulse width was first observed and its dependence on various factors is also discussed.

Key words: SET, pulsewidth, 65 nm



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图1.  Target circuit configuration (inverter target as an example)

Figure 1.


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图2.  Comparison of SET pulse width of INV and INV_LVT strings. (a) SET distribution as a function of pulse width when irradiated by Cl ions. (b) SET pulse width distribution at four different LETs

Figure 2.


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图3.  SET distribution observed in different logic gate strings for Ge at different temperature. "_NT" stands for 23 ℃ and "_HT" for 125℃. To simplify the $x$-axis,only the mean value is placed.

Figure 3.


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图4.  SET pulse width distribution of INV,NAND and NOR strings when stricken by Kr. A second peak in the distribution exists for all three logic gates.

Figure 4.


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图5.  Box plot representing the minimum,maximum and max-amount SET pulse widths for four different LETs for INV and INV_sw strings.

Figure 5.


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表1.   Different designs in target strings

Table 1.

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表2.   Ions used in this study

Table 2.

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    Received: 11 June 2015 Revised: Online: Published: 01 November 2015

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      Article Navigation >  Journal of Semiconductors  > 2015  >  36(11): 115006
      Suge Yue, Xiaolin Zhang, Xinyuan Zhao. Single event transient pulse width measurement of 65-nm bulk CMOS circuits[J]. Journal of Semiconductors, 2015, 36(11): 115006. doi: 10.1088/1674-4926/36/11/115006 S G Yue, X L Zhang, X Y Zhao. Single event transient pulse width measurement of 65-nm bulk CMOS circuits[J]. J. Semicond., 2015, 36(11): 115006. doi: 10.1088/1674-4926/36/11/115006.Export: BibTex EndNote
      Citation:
      Suge Yue, Xiaolin Zhang, Xinyuan Zhao. Single event transient pulse width measurement of 65-nm bulk CMOS circuits[J]. Journal of Semiconductors, 2015, 36(11): 115006. doi: 10.1088/1674-4926/36/11/115006

      S G Yue, X L Zhang, X Y Zhao. Single event transient pulse width measurement of 65-nm bulk CMOS circuits[J]. J. Semicond., 2015, 36(11): 115006. doi: 10.1088/1674-4926/36/11/115006.
      Export: BibTex EndNote
      shu

      Single event transient pulse width measurement of 65-nm bulk CMOS circuits

      doi: 10.1088/1674-4926/36/11/115006
      • 1.

        Beijing University of Aeronautics & Astronautics, Beijing 100191, China

      • 2.

        Beijing Microelectronics Technology Institute, Beijing 100076, China

      More Information
      • Corresponding author: Yue Suge, Email: yuesg9999@163.com
      • Received Date: 2015-06-11
      • Accepted Date: 2015-07-23
      • Published Date: 2015-01-25

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