J. Semicond. > 2008, Volume 29 > Issue 3 > 423-427

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A Novel Interconnect Crosstalk Parallel RLC Analyzable Model Based on the 65nm CMOS Process

Zhu Zhangming, Qian Libo and Yang Yintang

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Abstract: Based on the 65nm CMOS process,a novel parallel RLC coupling interconnect analytical model is presented synthetically considering parasitical capacitive and parasitical inductive effects.Applying function approximation and model order-reduction to the model,we derive a closed-form and time-domain waveform for the far-end crosstalk of a victim line under ramp input transition.For various interconnect coupling sizes,the proposed RLC coupling analytical model enables the estimation of the crosstalk voltage within 2.50% error compared with Hspice simulation in a 65nm CMOS process.This model can be used in computer-aided-design of nanometer SOCs.

Key words: nanometer CMOSinterconnect coupling crosstalkparallel RLC analytical modelparameter extractionfunction approximation

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    Received: 18 August 2015 Revised: 16 September 2007 Online: Published: 01 March 2008

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      Zhu Zhangming, Qian Libo, Yang Yintang. A Novel Interconnect Crosstalk Parallel RLC Analyzable Model Based on the 65nm CMOS Process[J]. Journal of Semiconductors, 2008, In Press. Zhu Z M, Qian L B, Yang Y T. A Novel Interconnect Crosstalk Parallel RLC Analyzable Model Based on the 65nm CMOS Process[J]. J. Semicond., 2008, 29(3): 423.Export: BibTex EndNote
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      Zhu Zhangming, Qian Libo, Yang Yintang. A Novel Interconnect Crosstalk Parallel RLC Analyzable Model Based on the 65nm CMOS Process[J]. Journal of Semiconductors, 2008, In Press.

      Zhu Z M, Qian L B, Yang Y T. A Novel Interconnect Crosstalk Parallel RLC Analyzable Model Based on the 65nm CMOS Process[J]. J. Semicond., 2008, 29(3): 423.
      Export: BibTex EndNote

      A Novel Interconnect Crosstalk Parallel RLC Analyzable Model Based on the 65nm CMOS Process

      • Received Date: 2015-08-18
      • Accepted Date: 2007-09-16
      • Revised Date: 2007-09-16
      • Published Date: 2008-02-28

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