SEMICONDUCTOR DEVICES

A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp

Hongwei Pan, Siyang Liu and Weifeng Sun

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 Corresponding author: Pan Hongwe, Email:phwseu@163.com

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Abstract: The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure, when used in power-rail ESD (electro-static discharge) clamp circuits. In order to eliminate latch-up risk, this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current. The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.

Key words: ESD protectionESD robustnessSCR-LDMOSlatch-upholding voltage



[1]
Vashchenko V A, Concannon A, Beekter M, et al. High holding voltage cascaded LVTSCR structures for 5.5 V tolerant ESD protection clamps. IEEE Trans Device Mater Reliab, 2004, 4(2):273 doi: 10.1109/TDMR.2004.826584
[2]
Miao M, Dong S, Li M, et al. Trigger voltage walk-in effect of ESD protection device in HVCMOS. IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010
[3]
Vashchenko V A, Concannon A, Beek M T, et al. Comparison of ESD protection capability of lateral BJT, SCR and bidirectional SCR for high-voltage BiCMOS circuits. IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2002
[4]
Keppens B, Mergens M P J, Cong S T, et al. ESD protection solutions for high voltage technologies. Electrical Overstress/Electrostatic Discharge Symposium, 2004
[5]
Pendharkar S, Teggatz R, Devore J, et al. SCR-LDMOS——a novel LDMOS device with ESD robustness. International Symposium on Power Semiconductor Devices and ICs, 2000
[6]
Liu Z, Liou J J, Vinson J. Novel silicon-controlled rectifier (SCR) for high-voltage electrostatic discharge (ESD) applications. IEEE Electron Device Lett, 2008, 29(7):753 doi: 10.1109/LED.2008.923711
[7]
Meneghesso G, Tazzoli A, Marino F A, et al. Development of a new high holding voltage SCR-based ESD protection structure. IEEE International Reliability Physics Symposium, 2008
[8]
Chen W Y, Ker M D. Improving safe operating area of nLDMOS array with embedded silicon controlled rectifier for ESD protection in a 24-V BCD process. IEEE Trans Electron Devices, 2011, 58(9):2944 doi: 10.1109/TED.2011.2159861
[9]
Ker M D, Lin K H. The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latch-free power-rail ESD clamp circuit for LCD driver ICs. IEEE J Solid-State Circuits, 2005, 40(8):1751 doi: 10.1109/JSSC.2005.852046
[10]
Gendron A, Salamero C. Area-efficient, reduced and no-snapback PNP-based ESD protection in advanced smart power technology. Electrical Overstress/Electrostatic Discharge Symposium, 2006
[11]
Lin K H, Ker M D. Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs. Electrical Overstress/Electrostatic Discharge Symposium, 2004
Fig. 1.  Cross section of (a) a conventional LDMOS, (b) an SCR-LDMOS, (c) an equivalent circuit conventional LDMOS, and (d) an SCR-LDMOS.

Fig. 2.  (a) Cross section of the proposed structure with NIL. (b) Top view of the layout structure.

Fig. 3.  Arsenic concentration in the NDD region for the typical SCR-LDMOS and the SCR-LDMSO with NIL.

Fig. 4.  Hole density of (a) the typical SCR-LDMOS and (b) the proposed structure.

Fig. 5.  Simulated $I$$V$ characteristics for the typical SCR-LDMOS (without NIL), the proposed structure with 2 $\mu$m, 1.6 $\mu$m and 1.2 $\mu$m NIL.

Fig. 6.  (a) Measurement setup of devices under TLP stresses. (b) TLP characteristic ($I$$V$ characteristics with corresponding leakage current) for the typical SCR-LDMOS (without NIL) and the optimum structure ($D_{\rm N}$ $=$ 2 $\mu$m).

Table 1.   ESD parameters and EV of various high holding voltage devices.

[1]
Vashchenko V A, Concannon A, Beekter M, et al. High holding voltage cascaded LVTSCR structures for 5.5 V tolerant ESD protection clamps. IEEE Trans Device Mater Reliab, 2004, 4(2):273 doi: 10.1109/TDMR.2004.826584
[2]
Miao M, Dong S, Li M, et al. Trigger voltage walk-in effect of ESD protection device in HVCMOS. IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010
[3]
Vashchenko V A, Concannon A, Beek M T, et al. Comparison of ESD protection capability of lateral BJT, SCR and bidirectional SCR for high-voltage BiCMOS circuits. IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2002
[4]
Keppens B, Mergens M P J, Cong S T, et al. ESD protection solutions for high voltage technologies. Electrical Overstress/Electrostatic Discharge Symposium, 2004
[5]
Pendharkar S, Teggatz R, Devore J, et al. SCR-LDMOS——a novel LDMOS device with ESD robustness. International Symposium on Power Semiconductor Devices and ICs, 2000
[6]
Liu Z, Liou J J, Vinson J. Novel silicon-controlled rectifier (SCR) for high-voltage electrostatic discharge (ESD) applications. IEEE Electron Device Lett, 2008, 29(7):753 doi: 10.1109/LED.2008.923711
[7]
Meneghesso G, Tazzoli A, Marino F A, et al. Development of a new high holding voltage SCR-based ESD protection structure. IEEE International Reliability Physics Symposium, 2008
[8]
Chen W Y, Ker M D. Improving safe operating area of nLDMOS array with embedded silicon controlled rectifier for ESD protection in a 24-V BCD process. IEEE Trans Electron Devices, 2011, 58(9):2944 doi: 10.1109/TED.2011.2159861
[9]
Ker M D, Lin K H. The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latch-free power-rail ESD clamp circuit for LCD driver ICs. IEEE J Solid-State Circuits, 2005, 40(8):1751 doi: 10.1109/JSSC.2005.852046
[10]
Gendron A, Salamero C. Area-efficient, reduced and no-snapback PNP-based ESD protection in advanced smart power technology. Electrical Overstress/Electrostatic Discharge Symposium, 2006
[11]
Lin K H, Ker M D. Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs. Electrical Overstress/Electrostatic Discharge Symposium, 2004
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    Received: 16 June 2012 Revised: 31 July 2012 Online: Published: 01 January 2013

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      Hongwei Pan, Siyang Liu, Weifeng Sun. A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp[J]. Journal of Semiconductors, 2013, 34(1): 014007. doi: 10.1088/1674-4926/34/1/014007 H W Pan, S Y Liu, W F Sun. A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp[J]. J. Semicond., 2013, 34(1): 014007. doi: 10.1088/1674-4926/34/1/014007.Export: BibTex EndNote
      Citation:
      Hongwei Pan, Siyang Liu, Weifeng Sun. A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp[J]. Journal of Semiconductors, 2013, 34(1): 014007. doi: 10.1088/1674-4926/34/1/014007

      H W Pan, S Y Liu, W F Sun. A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp[J]. J. Semicond., 2013, 34(1): 014007. doi: 10.1088/1674-4926/34/1/014007.
      Export: BibTex EndNote

      A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp

      doi: 10.1088/1674-4926/34/1/014007
      Funds:

      the Natural Science Foundation of Jiangsu Province BK2011059

      Project supported by the Natural Science Foundation of Jiangsu Province (No.BK2011059) and the Program for New Century Excellent Talent in University (No.NCET-10-0331)

      the Program for New Century Excellent Talent in University NCET-10-0331

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      • Corresponding author: Pan Hongwe, Email:phwseu@163.com
      • Received Date: 2012-06-16
      • Revised Date: 2012-07-31
      • Published Date: 2013-01-01

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